Abstract: Exemplary embodiments of the present invention are drawn to improved systems and process for anodically bonding multiple substrate wafers to each other at low temperatures. At least one circuit wafer having printed circuits thereon is bonded to an interposer wafer by applying an amorphous thin film between the wafers. A low voltage is applied across the wafers to heat the wafers and to cause bonding of the wafers. Multiple circuit and interposer wafers can be used. The bonding temperature is low enough that soldered connections on the circuit wafers will not flow or otherwise distort, thus maintaining electrical integrity.

Abstract: An semiconductor device having a plurality of fabrication layers. A first region of a first fabrication layer of the semiconductor device is revised. To signal the revision, a connectivity structure in a second region of the first fabrication layer is omitted to interrupt an otherwise continuous signal path that extends through a plurality of interconnection layers of the semiconductor device.

Abstract: The purpose of the invention is to improve reliability of a light emitting apparatus comprising TFTs and organic light emitting elements.

Abstract: A method of manufacturing a semiconductor device includes the steps of providing a semiconductor substrate (202), forming a dielectric layer (204) over the semiconductor substrate (202), and etching a trench or a via (206) in the dielectric layer (204) to expose a portion of the surface of the semiconductor substrate (202). The method also includes the step of forming a conductive layer (212, 220) within in the trench or the via (206). The method further includes the steps of polishing a portion of the conductive layer (220) and annealing the conductive layer (212, 220) at a predetermined temperature. Moreover, the conductive layer (212, 220) also includes a dopant, and the dopant diffuses substantially to the surface of the top side of the conductive layer (212, 220) to form a dopant oxide layer (212a, 220a) when the conductive layer (212, 220) is annealed at the predetermined temperature and the dopant is exposed to oxygen.

Abstract: A power chip set for a switching mode power supply includes a high voltage chip and a control unit chip. The high voltage chip contains a switching power metal-oxide-semiconductor (MOS) transistor being turned on/off under control of an output signal from the control unit, and a junction field effect transistor (JFET) coupled between a drain of the switching power MOS transistor and a power terminal of the control unit to serve as a start up element for driving the control unit during initiation, in which the JFET has a negative threshold voltage and the absolute value thereof is equal to the voltage for driving the control unit. The JFET structure in the high voltage chip further includes a Zener diode for over voltage protection of the control unit. The high voltage chip further contains a current-sense power MOS transistor coupled with the drain of the switching power MOS transistor for detecting a drain current of the switching power MOS transistor. The chip set can be packaged into a power module.

Abstract: A semiconductor device includes a resin housing provided with a functional part, a wire pattern made of a conductive material and molded in the resin housing, a part of the wire pattern being exposed from the resin housing, an electronic part connected with the wire pattern in a state where the electronic parts is molded in the resin housing, and a semiconductor element connected to the part of the wire pattern being exposed from the resin housing. The semiconductor element provides a designated function in cooperation with a functional part of the resin housing.

Abstract: Devices that have bonding pads, and methods for fabricating the same. The bonding pads have two conductive layers, and an intermediate layer between them. The intermediate layer has a hybrid configuration of a relatively large conductive plate section, and a mixed plugs/mesh section. The plugs/mesh section has conductive portions interspersed with non-conducting portions, with features that are relatively small in size. The hybrid configuration achieves a proper balance between the plate section for the main electrical contact, and the plugs/mesh section for support and additional current density.

Abstract: In a resin-sealed laser diode device, in order to prevent the sealing resin on the front light-emitting end face of the laser diode chip from being deteriorated by the laser beam, a thermosetting rubber-like organic silicone resin layer is formed on the front light-emitting end face to a thickness of at least 50 &mgr;m on the extension of the surface of the active layer. On the side of the rear light-emitting end-face of the laser diode chip, the rubber-like organic silicone resin layer on the photo-diode is curved upwardly with respect to the light receiving surface of the latter. Furthermore, in order to prevent the far field pattern of the laser beam from being made irregular, at least the surface of the end-face protecting film on the light-emitting end face essentially contains silicon dioxide.

Abstract: An improved arrangement for attaching a heat sink to a flip chip type die is disclosed. More specifically, the heat sink is attached to the back surface of the flip chip die by a metallic solder material. Such an arrangement provides a good thermal conductivity between the die and the heat sink. In some embodiments, the die is mounted on a grid array type substrate in a flip chip arrangement such that the die contacts are coupled to adjacent I/O pads on the substrate. In another aspect, one or more metallic intermediate die attach layers are deposited over the back surface of the die to form a solderable die surface. The heat sink is then attached to the solderable die surface. This approach works well when the chosen solder does not adhere well to the semiconductor die material. In one preferred implementation the intermediate metallic layers include a barrier layer that is deposited over the back surface of the die and a solderable metallic layer that is deposited over the barrier layer.

Abstract: A scalable multi-power integrated circuit package for integrated circuits having spaced apart first, second and third pluralities of respective spaced apart chip power bonding pads connected to corresponding first, second, and third chip power supply nets, the chip power bonding pads disposed adjacent to a chip periphery defining the chip area, the scalable multi-power integrated circuit package comprising: a central chip mounting area for mounting one of said integrated circuits, said chip mounting area defining a chip mounting area periphery surrounding said chip mounting area; spaced apart first, second and third package power supply continuous conductive traces, each trace disposed adjacent to the chip area mounting periphery; corresponding first, second and third pluralities of spaced apart package bonding areas defined along each respective one of said first, second and third package power supply continuous conductive traces, each respective one of said package bonding areas disposed in bondable alignme

Abstract: A solder ball pad for mounting and connecting of electronic devices and, more particularly, apparatus and methods providing an improved solder ball pad structure on a substrate, such as a printed circuit board (“PCB”) or a semiconductor die, while enabling better use of the spaces between adjacent solder ball pads and at the same time providing increased surface area for bonding to a solder ball. Substrates, electronic device assemblies and systems incorporating the invention are also disclosed.

Abstract: A noise eliminating system on chip and method of fabricating the same are provided. A noise eliminating system is connected to a chip. There are guiding units provided on the chip for connecting with the noise eliminating system, thereby reducing simultaneous switching noise of the chip.

Abstract: A semiconductor device has a via-contact, a main wire having an end connected to the via-contact, and an extension extended in line with the main wire from the end of the main wire beyond the via-contact, the width of the extension being equal to or narrower than the width of the main wire. The extension prevents the end of the main wire from being rounded by an optical proximity effect, eliminates a contact defect or an open defect between the via-contact and the end of the main wire, and involves no widening of the main wire around the via-contact, so that other via-contacts may be arranged in the vicinity of the via-contact in question without violating design rules.

Abstract: A ceramic substrate in which even if rapid temperature rising or rapid temperature falling is conducted, no problem of cracking or warp of the ceramic substrate occurs. In a case that the ceramic substrate is a ceramic substrate constituting an electrostatic chuck, local dispersion of chuck power is eliminated, in a case that the ceramic substrate is a ceramic substrate constituting a hot plate, local dispersion of temperature of a wafer treating face is eliminated, and in a case that the ceramic substrate is a ceramic substrate constituting a wafer prober, dispersion of applied voltage of a guard electrode or a ground electrode is eliminated and a stray capacitor or noise can be eliminated. The ceramic substrate is provided with a conductor layer on the surface of the ceramic substrate or inside the ceramic substrate. A ratio (t2/t1) of the average thickness of the conductor layer (t2) to the average thickness of the ceramic substrate (t1) is less than 0.

Abstract: The present invention relates to an improved method for forming a UBM pad and solder bump connection for a flip-chip which eliminates at least two mask steps required in standard UBM pad forming processes when repatterning the bond pad locations.

Abstract: A mark configuration is provided for the orientation and/or determination of the relative position of a substrate and/or of layers on the substrate during a lithographic exposure, in particular for the case of a wafer during the fabrication of DRAMs. At least one part of a mark is disposed above a patterned background for the purpose of increasing a difference in contrast between the mark and the substrate. A wafer can also be manufactured with such a mark configuration. A method for fabricating the mark configuration is also described. An efficient and simple orientation of layers and/or of the substrate is thus made possible.

Abstract: A substrate 10 includes multiple layers mounted with a mounted part 20 at its surface. A part pad 40 is provided to the substrate 10 to correspond to an electrode of the mounted part 20. A circuit pattern is provided at a layer at an inner portion of the substrate and an electrically conductive portion 60 for electrically connecting the part pad 40 and the circuit pattern right under the part pad 40.

Abstract: A multichip semiconductor package device includes first and second devices and a conductive bond. The first device includes an insulative housing, a first semiconductor chip and a conductive trace. The first insulative housing includes a peripheral ledge and a central portion that is recessed relative to the peripheral ledge, and the peripheral ledge and the central portion form a cavity. The conductive trace includes a terminal that extends through the central portion and a lead that protrudes laterally from and extends through the side surface. The second device includes a second semiconductor chip, extends into the cavity and is positioned within and does not extend outside a periphery of the cavity. The conductive bond is inside the cavity, on the terminal and contacts and electrically connects the first and second devices.

Abstract: A semiconductor device (10) having a gate (15), a source (19), and a drain (20) with a gate bus (25) and first ground shield (24) patterned from a first metal layer and a second ground shield (31) patterned from a second metal layer. The first ground shield (24) and the second ground shield (31) lower the capacitance of device (10) making it suitable for high frequency applications and housing in a plastic package.

Abstract: Disclosed is a solid state image sensing device. The solid state image sensing device comprises a semiconductor chip for image sensing which has at least one of photoelectric conversion element line; and a package into which the semiconductor chip is received. The package is composed of an insulating package body which has the semiconductor chip mounted on a flat inner bottom surface of a concave portion; a transparent cover glass to be fixed on an upper surface of an outer frame of the concave portion for sealing the concave portion; and a lead frame which is brought out to the outside of the package body. The solid state image sensing device has a reference plane for attaching onto an image input apparatus is arranged on the package. The reference plane for attaching is made parallel to the inner bottom surface of the concave portion on which the semiconductor chip is mounted.