Abstract: A plasma processing device, a plasma processing method and a manufacturing method of an electronic device with excellent uniformity, are capable of performing heating and high-speed processing for a short period of time as well as controlling the distribution of heating performances in a linear direction (amounts of heat influx to a substrate). In an inductively-coupled plasma torch unit, coils, a first ceramic block and a second ceramic block are arranged, and a chamber has an annular shape. A plasma P is applied to a substrate at an opening of the chamber. The chamber and the substrate are relatively moved in a direction perpendicular to a longitudinal direction of the opening. Plural gas jetting ports jetting a gas toward a substrate stage are provided side by side in a direction of a line formed by the opening, thereby controlling the distribution of heating performances in the linear direction and realizing plasma processing with excellent uniformity.

Abstract: A method of making a spin-torque transfer magnetic random access memory device (STT MRAM) device includes forming a tunnel barrier layer on a reference layer; forming a free layer on the tunnel barrier layer, the free layer comprising a cobalt iron boron (CoFeB) alloy layer and an iron (Fe) layer; and performing a sputtering process to form a metal oxide layer on the Fe layer.

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device comprises a first multi-channel active pattern which is defined by a field insulating layer, extends along a first direction, and includes a first portion and a second portion; a gate electrode which extends along a second direction different from the first direction and is formed on the first portion; and a first source/drain region which is formed around the second portion protruding further upward than a top surface of the field insulating layer and contacts the field insulating layer, wherein the second portion is disposed on both sides of the first portion in the first direction and is more recessed than the first portion, a top surface of the first portion and a top surface of the second portion protrude further upward than the top surface of the field insulating layer, and a profile of sidewalls of the second portion is continuous.

Abstract: A number of micro-sized rectangular dot-like n-type semiconductor regions 121 are created in a p-type semiconductor region which is a base body 11. Contact parts 14, each of which is in contact with one n-type semiconductor region 121 and almost entirely covers the same region, are mutually connected by a wire part 15 as a common cathode terminal. The n-type semiconductor regions 121 receives no light; their function is to collect carriers generated within and outside the surrounding depletion layers. Appropriate setting of the spacing of the n-type semiconductor regions 121 enables efficient collection of the carriers generated in the p-type semiconductor region while improving the SN ratio of the photo-detection signal by a noise-reduction effect due to a decrease in the p-n junction capacitance. Carriers originating from light of shorter wavelengths are barely reflected in the photo-detection signal. Thus, unfavorable influences of the shorter wavelengths of light are eliminated.

Abstract: Provided is a semiconductor device having a light receiving element in which a plurality of photodiodes are formed on a top surface of a P-type semiconductor substrate, an insulating oxide film is formed on surfaces of the photodiodes 51 via a buried oxide film, and an SOI layer of single crystal silicon is formed between a photodiode and an adjacent photodiode via the buried oxide film for shielding unnecessary light.

Abstract: A vertical transistor includes a semiconductor substrate, and fin(s) over the semiconductor substrate (n-type fin(s) and/or p-type fin(s)), the fin(s) acting as vertical transistor channels for vertical transistors. Each of the fin(s) is lattice mismatched at one or more interface(s), being stressed from below, from above, from fin sidewalls or combination(s) thereof. The vertical transistors can be realized by providing a semiconductor substrate, forming stressed fin(s) of vertical transistor(s) acting as vertical transistor channels, the stressed fin(s) being lattice mismatched at one or more interfaces and being stressed from below, above, sidewalls or combination(s) thereof.

Abstract: A display panel including first and second sub pixel electrodes, a first light emitting unit, first and second charge generation layers, a second light emitting unit, and an upper electrode. The first light emitting unit is provided with a first contact hole. The first charge generation layer includes a first contact part being in the first contact hole and coupled to a portion of the first sub pixel electrode exposed by the first contact hole, and a first extension part extending from the first contact part and being on the first light emitting unit. The second charge generation layer and the second light emitting unit are provided with a second contact hole. The upper electrode includes a first upper electrode part being in the second contact hole and coupled to a second contact part of the second charge generation layer exposed by the second contact hole.

Abstract: A pixel structure for use in a high-definition light-emitting display panel having a plurality of sub-pixels, comprising: a glass substrate; a backplane that is disposed on the glass substrate and includes a capacitive element having sufficiently high light transmittance to cause 50 percent or more of light to be transmitted therethrough; a frontplane that is disposed on the backplane and includes a light-emitting element disposed so as to radiate light towards the glass substrate and the backplane; an electrical connecting portion that provides an electrical connection between the frontplane and the backplane, three or fewer of such electrical connecting portions being provided on one of the sub-pixels; and a switching element that is provided on the backplane and controls electricity distribution to the light-emitting element, wherein an aperture ratio from which light is transmitted through the glass substrate is 20 percent or more.

Abstract: A radiation tolerant optical detection element includes: a p-type base-body region; a gate insulating film provided on an upper surface of the base-body region; an n-type buried charge-generation region buried in an upper portion of the base-body region; an n-type charge-readout region buried in an upper portion of the base-body region on the inner-contour side of the buried charge-generation region; an n-type reset-drain region buried on the inner-contour side of the charge-readout region; a transparent electrode provided on the gate insulating film above the buried charge-generation region; and a reset-gate electrode provided on a portion of the gate insulating film between the charge-readout region and the reset-drain region.

Abstract: A semiconductor element having high mobility, which includes an oxide semiconductor layer having crystallinity, is provided. The oxide semiconductor layer includes a stacked-layer structure of a first oxide semiconductor film and a second oxide semiconductor film having a wider band gap than the first oxide semiconductor film, which is in contact with the first oxide semiconductor film. Thus, a channel region is formed in part of the first oxide semiconductor film (that is, in an oxide semiconductor film having a smaller band gap) which is in the vicinity of an interface with the second oxide semiconductor film. Further, dangling bonds in the first oxide semiconductor film and the second oxide semiconductor film are bonded to each other at the interface therebetween. Accordingly, a decrease in mobility resulting from an electron trap or the like due to dangling bonds can be reduced in the channel region.

Abstract: The present invention relates generally to a semiconductor device, and more particularly, to a structure and method of forming a compressive strained layer and a tensile strained layer on the same wafer. A lower epitaxial layer may be formed adjacent to a tensile strained layer. An upper epitaxial layer may be formed over a portion of the lower epitaxial layer. Thermal oxidation may convert the upper epitaxial layer to an upper oxide layer, and thermal condensation may causes a portion of the lower epitaxial layer to become a compressive strained layer. The upper oxide layer and a remaining portion of the lower epitaxial layer may be removed, leaving the tensile strained layer and the compressive strained layer.

Abstract: Methods and apparatuses for selectively depositing silicon nitride on silicon surfaces relative to silicon oxide surfaces and selectively depositing silicon nitride on silicon oxide surfaces relative to silicon surfaces are provided herein. Methods involve exposing the substrate to an alkene which is selectively reactive with the silicon surface to block the silicon surface by forming an organic moiety on the silicon surface prior to depositing silicon nitride selectively on silicon oxide surfaces using thermal atomic layer deposition. Methods involve exposing the substrate to an alkylsilylhalide which is selectively reactive with the silicon oxide surface to block the silicon oxide surface by forming an organic moiety on the silicon oxide surface prior to depositing silicon nitride selectively on silicon surfaces using thermal atomic layer deposition.

Abstract: A method for co-integrating wimpy and nominal devices includes growing source/drain regions on semiconductor material adjacent to a gate structure to form device structures with a non-electrically active material. Selected device structures are masked with a block mask. Unmasked device structures are selectively annealed to increase electrical activity of the non-electrically active material to adjust a threshold voltage between the selected device structures and the unmasked device structures.

Abstract: In some examples, device includes an integrated circuit (IC) inside a first insulating layer, an inductor, and a second insulating layer arranged between the first insulating layer and the inductor. The first insulating layer shares an interface with the second insulating layer, and the inductor is attached to the second insulating layer. The device further includes a conductive path configured to conduct electricity between the IC and the inductor, wherein the conductive path is inside the second insulating layer.

Abstract: Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes depositing a first conductive material comprising nickel on a first conductive surface of a first die, and depositing a second conductive material comprising nickel on a second conductive surface of a second die spaced apart from the first surface. The method further includes depositing a third conductive material on the second conductive material, and thermally compressing tin/solder between the first and third conductive materials to form an intermetallic palladium joint that extends between the first conductive material and the second conductive material such that one end of the intermetallic palladium joint is bonded directly to the first conductive material and an opposite end of the intermetallic palladium joint is bonded directly to the second conductive material.

Abstract: The semiconductor device according to the present invention has an upper electrode, a first lower layer wiring that also functions as a lower electrode, an electrical resistance-changing film interposed between the upper electrode and the first lower layer wiring, a second lower layer wiring, and a contact plug, the contact plug connecting to the upper electrode and to the second lower layer wiring. The present invention yields a semiconductor device with which it is possible to dispose elements in high density while maintaining the reliability and manufacturing yield of the electrical resistance-changing element.

Abstract: A method of forming a wafer level chip scale package interconnect may include: forming a post-passivation interconnect (PPI) layer over a substrate; forming an interconnect over the PPI layer; and releasing a molding compound material over the substrate, the molding compound material flowing to laterally encapsulate a portion of the interconnect.

Abstract: The present invention relates generally to a semiconductor device, and more particularly, to a structure and method of forming a compressive strained layer and a tensile strained layer on the same wafer. A lower epitaxial layer may be formed adjacent to a tensile strained layer. An upper epitaxial layer may be formed over a portion of the lower epitaxial layer. Thermal oxidation may convert the upper epitaxial layer to an upper oxide layer, and thermal condensation may causes a portion of the lower epitaxial layer to become a compressive strained layer. The upper oxide layer and a remaining portion of the lower epitaxial layer may be removed, leaving the tensile strained layer and the compressive strained layer.

Abstract: The invention discloses a quantum dot composite fluorescent particle including quantum dots, a mesoporous material, and a water-blocking and oxygen-blocking material. The quantum dots are distributed in the mesoporous material, and the water-blocking and oxygen-blocking material is filled in the gaps between the quantum dots and the mesoporous material. The quantum dot composite fluorescent particles may also include metal nanoparticles distributed within the mesoporous material and/or a blocking layer coating the outer surface of the mesoporous material. These features greatly improve the water and oxygen blocking properties and thus, the stability of the quantum dot composite fluorescent particles. The metal nanoparticles help the quantum dots capture more blue lights due to the localized surface resonance plasma and consequently improve the utilization ratio of the blue lights. The quantum dot composite fluorescent particle can then be integrated into an LED module to improve its service life.

Abstract: An electronic package includes an adhesion layer between a first substrate and a second substrate. The adhesion layer is patterned to define openings aligned with through-substrate interconnects and corresponding bond pads. A conductive plane is formed between the first substrate and the second substrate, adjacent to the adhesion layer.