Abstract: A cutting method includes: forming a reformed region in a workpiece; and after forming the reformed region in the workpiece, forming a groove in the workpiece along an intended cut line. In the forming a groove, a first dry etching process is performed from a front surface toward a rear surface of the workpiece. After the first dry etching process, a first pressure-reducing process is performed in which the workpiece is placed under an atmosphere of reduced pressure as compared to pressure during the first dry etching process. After the first pressure-reducing process, a second dry etching process is performed from the front surface toward the rear surface of the workpiece.

Abstract: A method for transferring, from a donor substrate to a carrier substrate, a thin layer having a first coefficient of thermal expansion. This method comprises: —forming an embrittlement plane in the donor substrate; —forming an electrically insulating layer on the surface of the donor substrate and/or of the carrier substrate; —producing an assembly by placing the donor substrate and the carrier substrate in contact with one another via the insulating layer; —separating the assembly by fracturing along the embrittlement plane.

Abstract: A sensor may be provided, including a substrate having a first semiconductor layer, a second semiconductor layer, and a buried insulator layer arranged between the first semiconductor layer and the second semiconductor layer. The sensor may further include a photodiode arranged in the first semiconductor layer; and a quenching resistive element electrically connected in series with the photodiode. The quenching resistive element is arranged in the second semiconductor layer, and the quenching resistive element is arranged over the photodiode but separated from the photodiode by the buried insulator layer.

Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer, a bottom electrode over the Nth metal layer, a magnetic tunneling junction (MTJ) over the bottom electrode, a top electrode over the MTJ, and an (N+M)th metal layer over the Nth metal layer. N and M are positive integers. The (N+M)th metal layer surrounds a portion of a sidewall of the top electrode. A manufacturing method of forming the semiconductor structure is also provided.

Abstract: Provided are a display panel, a display device and a method for manufacturing a display panel. The display panel includes a display area including a first display area and a second display area. The second display area is multiplexed as a sensor reserved area. The second display area includes a light transmitting area and a light emitting area. The first display area is provided with a plurality of organic light emitting units. The light emitting area of the second display area is provided with a plurality of Micro LEDs. The second display area is further provided with a wall structures disposed in gaps between the plurality of Micro LEDs and the plurality of organic light emitting units and gaps between adjacent ones of the plurality of Micro LEDs.

Abstract: A leadframe includes a first die attach pad (“DAP”) having a first longitudinally extending edge surface and a second DAP having a first longitudinally extending edge surface. The second DAP is positioned with the first longitudinally extending edge surface thereof in adjacent, laterally and vertically spaced relationship with the first longitudinally extending edge surface of the first DAP.

Abstract: A display apparatus includes a substrate including a first subpixel and a second subpixel, a first electrode including a first sub-electrode provided in the first subpixel and a second sub-electrode provided in the second subpixel, the first electrode being provided on the substrate, an organic light emitting layer on the first electrode, a second electrode on the organic light emitting layer, a first bank between the first sub-electrode and the second sub-electrode, the first bank dividing the first subpixel and the second subpixel, a color filter layer on the second electrode, a reflective metal at a portion of the color filter layer, and a light absorbing part on an upper surface of the reflective metal, the light absorbing part absorbing light, wherein the first electrode is provided as a reflective electrode, and the organic light emitting layer is disposed between the reflective electrode and the reflective metal.

Abstract: A display device with a through-hole that can prevent external moisture or oxygen from permeating into a light emitting element. The display device with a through-hole includes a substrate including a display area in which pixels are disposed and a non-display area surrounding the display area, and further including a through-hole in the display area, a first dam surrounding the through-hole, a first conductive line provided along the first dam between the first dam and the pixels, and a second conductive line provided along the first dam between the first dam and the through-hole.

Abstract: A method of forming the fin structure that includes forming a replacement gate structure on a channel region of the at least one replacement fin structure; and forming an encapsulating dielectric encapsulating the replacement fin structure leaving a portion of the replacement gate structure exposed. The exposed portion of the replacement gate structure is etched to provide an opening through the encapsulating dielectric to the replacement fin structure. The replacement fin structure is etched selectively to the dielectric to provide a fin opening having a geometry dictated by the encapsulating dielectric. Functional fin structures of a second semiconductor material is epitaxially grown on the growth surface of the substrate substantially filling the fin opening.

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure including a programmable logic device, an array of static random-access memory (SRAM) cells, and a first bonding layer including a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of NAND memory cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

Abstract: The present invention provides a chip carrier structure including: a non-circuit substrate, a plurality of micro heaters, and an adhesive layer. The micro heaters are disposed on the non-circuit substrate. The adhesive layer is disposed on the micro heaters, and a plurality of chips are disposed on the adhesive layer. Thereby, the present invention improves the solder yield of the process by a wafer carrying structure and a wafer carrying device.

Abstract: Semiconductor package structures are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon.

Abstract: A method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. The second redistribution lines are formed using the alignment mark for alignment.

Abstract: The present invention provides a film-shaped firing material 1 including sinterable metal particles 10, and a binder component 20, in which a content of the sinterable metal particles 10 is in a range of 15% to 98% by mass, a content of the binder component 20 is in a range of 2% to 50% by mass, a tensile elasticity of the film-shaped firing material at 60° C. is in a range of 4.0 to 10.0 MPa, and a breaking elongation thereof at 60° C. is 500% or greater; and a film-shaped firing material with a support sheet including the film-shaped firing material 1 which contains sinterable metal particles and a binder component, and a support sheet 2 which is provided on at least one side of the film-shaped firing material, in which an adhesive force (a2) of the film-shaped firing material to the support sheet is smaller than an adhesive force (a1) of the film-shaped firing material to a semiconductor wafer, the adhesive force (a1) is 0.1 N/25 mm or greater, and the adhesive force (a2) is in a range of 0.1 N/25 mm to 0.

Abstract: After a MISFET is formed on a substrate including a semiconductor substrate, an insulating layer and a semiconductor layer, an interlayer insulating film and a first insulating film are formed on the substrate. Also, after an opening is formed in each of the first insulating film and the interlayer insulating film, a second insulating film is formed at each of a bottom portion of the opening and a side surface of the opening and also formed on an upper surface of the first insulating film. Further, each of the second insulating film formed at the bottom portion of the opening and the second insulating film formed on the upper surface of the first insulating film is removed by etching. After that, an inside of the opening is etched under a condition that each of the first insulating film and the second insulating film is less etched than the insulating layer.

Abstract: A semiconductor device includes first and second nanowire structures, first and second annular hafnium oxide layers, first and second annular cap layers, and first and second metal gate electrodes. The first and second nanowire structures are suspended over a substrate and respectively have an n-channel region and a p-channel region. The first and second annular hafnium oxide layers encircle the n-channel region and the p-channel region, respectively. The first and second annular cap layers encircle the first and second annular hafnium oxide layers, respectively. The first and second annular cap layers are made of a same material that is lanthanum oxide, yttrium oxide, or strontium oxide. The first and second metal gate electrodes encircle the first and second annular cap layers, respectively. The first and second metal gate electrodes have a same metal composition.

Abstract: An electronic device includes a substrate, a grid structure, and a plurality of polarizing wires. The grid structure is disposed on the substrate and includes a plurality of apertures. The polarizing wires are disposed on the substrate and extend across the apertures. A first number of a portion of the polarizing wires within a first aperture of the apertures is in a range from 50 to 15000.

Abstract: Embodiments of the present disclosure describe techniques for fabricating a stacked integrated circuit (IC) device. A first wafer that includes a plurality of first IC dies may be sorted to identify first known good dies of the plurality of first IC dies. The first wafer may be diced to singulate the first IC dies. A second wafer that includes a plurality of second IC dies may be sorted to identify second know good dies of the plurality of second IC dies. The first known good dies may be bonded to respective second known good dies of the second wafer. In some embodiments, the first known good dies may be thinned after bonding the first know good dies to the second wafer. Other embodiments may be described and/or claimed.

Abstract: A process for fabricating an integrated circuit is provided, including steps of providing a substrate including a silicon layer, a layer of insulator a layer of hard mask and accesses to first and second regions of the silicon layer; forming first and second deposits of SiGe alloy on the first and the second regions in order to form first and second stacks; then protecting the first deposit and maintaining an access to the second deposit; then performing an etch in order to form trenches between the hard mask and two opposite edges of the second stack; then forming a tensilely strained silicon layer in the second region via amorphization of the second region; then crystallization; and enriching the first region in germanium by diffusion from the first deposit.

Abstract: A display panel includes an insulating substrate in which at least one hole is defined, wherein the insulating substrate comprises a hole area in which the hole is defined, a display area surrounding the hole area, and a peripheral area adjacent to the display area, a plurality of pixels in the display area, a plurality of main signal lines in the display area and electrically connected to the pixels, and a plurality of sub-signal lines in the hole area and electrically connected to the pixels, wherein the hole area comprises a line area which surrounds the hole and in which the sub-signal lines are located, and a compensation area between the line area and the display area in a plan view and configured to display a black color.