Abstract: A method for producing a stable sandwich arrangement of two components with solder situated therebetween, comprising the steps: (1) providing two components, each having at least one contact surface, and a free solder preform, (2) producing a sandwich arrangement of the components and a solder preform arranged between them and thus not yet connected to them by bringing into contact (i) each one of the contact surfaces, (ii) each of the single contact surface of the components or (iii) one of the contact surfaces of one component and a single contact surface of the other component, with the contact surfaces of the free solder preform, and (3) hot-pressing the sandwich arrangement produced in step (2) so as to form the stable sandwich arrangement at a temperature being at 10 to 40% below the melting temperature of the solder metal of the solder preform, expressed in ° C.

Abstract: A method to manufacture a semiconductor package includes: preparing a metal substrate; attaching semiconductor dies to the metal substrate at an interval; attaching a bonding film to the semiconductor dies; applying a mold material on the semiconductor dies and the metal substrate, and curing the mold material to form a mold member; grinding the mold member and the metal substrate to a thickness; removing the bonding film; attaching a redistribution layer to the semiconductor dies; and cutting between the semiconductor dies.

Abstract: The method of manufacturing a light emitting module includes: providing a light guiding plate having a first main surface serving as a light emitting surface; and a second main surface positioned opposite to the first main surface and provided with a recess; providing a light adjustment portion containing a fluorescent material; providing a light emitting element unit in which a light emitting element comprising an electrode is integrally bonded to the light adjustment portion; bonding the light adjustment portion of the light emitting element unit to the recess; and forming wiring on the electrode of the light emitting element.

Abstract: An integrated circuit includes a first set of fins, a second set of fins, a gate, and a dielectric plug. The second set of fins is discrete from the first set of fins, and the gate passes over the first set of fins and the second set of fins. The dielectric plug is surrounded by the gate on two sides where the gate passes between the first set of fins and the second set of fins. Incorporation of aspects of the invention into integrated circuits with fin-based field effect transistors (FinFETs) helps to reduce parasitic capacitance between gate features and other nearby electrically conductive features.

Abstract: A package structure of a power converter, can include: a die pad; an insulation adhesive layer and a conductive adhesive layer on the die pad; a control circuit die on the insulation adhesive layer, where the insulation adhesive layer comprises a first insulation adhesive layer on a back surface of the control circuit die, and a second insulation adhesive on a surface of the die pad, where the first insulation adhesive layer is connected to the second insulation adhesive layer; and a power device die on the conductive adhesive layer, where the insulation adhesive layer is separated from the conductive adhesive layer.

Abstract: A pixel array substrate includes signal lines, pixel structures, a driving element, a first fan-out trace and a second fan-out trace. The first fan-out trace includes a first segment connected to the driving element, a second segment connected to the first segment, and a third segment connected to the second segment. In the first fan-out trace, the sheet resistances of the first segment and the third segment are smaller than sheet resistance of the second segment. The second fan-out trace includes a first segment connected to the driving element and a second segment connected to the first segment. In the second fan-out trace, the first segment and the second segment are disposed correspondingly to the first segment and the two second segment and third segment, respectively. In the second fan-out trace, the sheet resistance of the second segment is less than the sheet resistance of the first segment.

Abstract: A display device includes a pixel array, multiple data lines and multiple gate lines. The pixel array includes multiple pixels. At least one of the pixels includes a first sub-pixel and a second sub-pixel. The first sub-pixel includes a pixel circuit, which includes a first light-emitting element and a first driving circuit. The first driving circuit is coupled to and configured to control the first light-emitting element. The first driving circuit includes multiple TFTs. The second sub-pixel includes a pixel circuit, which includes a second light-emitting element and a second driving circuit. The second driving circuit is coupled to and configured to control the second light-emitting element. The second driving circuit includes multiple TFTs. The number of TFTs of the first driving circuit and the number of TFTs of the second driving circuit are different.

Abstract: Low-cost and high-efficiency monolithically integrated nanoscale-based light emitter techniques can be used in, for example, electronic display applications and spectroscopy applications using spectrometers. Using various techniques, a light emitter can include quantum dots (QDs) and can be arranged to emit light in mono-band (e.g., one wavelength) or in broad-band (e.g., more than one wavelength) such as in the visible to mid-infrared range, e.g., from about 365 nm to about 10 ?m. The light emitter nanotechnology can be based on a nanoscale wafer manufacturing for displays and spectroscopy applications.

Abstract: A method for manufacturing a power semiconductor device includes forming a trench in a semiconductor substrate, forming a gate insulation film and a gate electrode in the trench, implanting a first conductivity type impurity into the semiconductor substrate to form a first conductivity type body region, implanting a second conductivity type impurity onto a surface of the semiconductor substrate to form a second conductivity type source region, forming an interlayer insulation film in the trench, implanting the first conductivity type impurity onto the surface of the semiconductor substrate to form a first conductivity type highly doped body contact region, exposing a portion of a side surface of the trench, and forming a source metal to be in contact with the exposed side surface of the trench.

Abstract: Anisotropic conductive film produced that a light-transmitting transfer die having openings with conductive particles disposed therein is prepared, and photopolymerizable insulating resin squeezed into openings to transfer conductive particles onto the surface of the photopolymerizable insulating resin layer, first connection layer is formed which has a structure in which conductive particles are arranged in a single layer in a plane direction of photopolymerizable insulating resin layer and the thickness of photopolymerizable insulating resin layer in central regions between adjacent ones of the conductive particles is smaller than thickness of photopolymerizable insulating resin layer in regions in proximity to conductive particles; first connection layer is irradiated with ultraviolet rays through light-transmitting transfer die; release film is removed from first connection layer; second connection layer is formed on the surface of first connection layer opposite to light-transmitting transfer die; and th

Abstract: A memory device is disclosed that includes memory cell, e strap cell, conductive segment, and logic cell. The strap cell is arranged abutting the memory cell. The strap cell includes an active region, a first gate, and a second gate. The first gate is arranged across the active region. The second gate is arranged across the active region and disposed at the end of active region. The conductive segment is disposed over the first gate and the second gate. The strap cell is disposed between the memory cell and the logic cell, and the logic cell includes a third gate. The conductive segment is spaced apart from the third gate, and the length of the conductive segment is smaller than five times of a gate pitch between the first gate and the second gate.

Abstract: A photodiode with a lens cap is provided, having a header with a photodiode active surface area where the photodiode active surface area has a diameter dF. Further included is a cap having a fused-in lens, the fused-in lens having a diameter dL shown in a top plan view of the cap. The ratio of the diameter of the fused-in lens to the diameter of the photodiode active surface area, dL/dF, is greater than 30.

Abstract: Overmolded microelectronic packages containing knurled base flanges are provided, as are methods for producing the same. In various embodiments, the overmolded microelectronic package includes a molded package body, at least one microelectronic device contained in the molded package body, and a base flange to which the molded package body is bonded. The base flange includes, in turn, a flange frontside contacted by the molded package body, a device attachment region located on the flange frontside and to which the at least one microelectronic is mounted, and a knurled surface region. The knurled surface region includes a first plurality of trenches formed in the base flange and arranged in a first repeating geometric pattern. The molded package body extends or projects into the first plurality of trenches to decrease the likelihood of delamination of the molded package body from the base flange.

Abstract: Implementations of the disclosed subject matter provide a print bar for organic vapor jet (OVJP) deposition is provided that includes a plurality of n print head segments, where each of the plurality of print head segments may have an OVJP print head. The print bar may include a plurality of distance sensors, where each of the plurality of distance sensors may be configured to measure a distance between a substrate disposed below the print bar and a portion of at least one of the print head segments. The print bar may include a plurality of not more than n+1 actuators configured to adjust at least one of a position and an orientation of one or more of the plurality of print head segments based upon one or more distances between the substrate and the print bar measured by one or more of the plurality of distance sensors.

Abstract: Disclosed is a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes forming a p-channel over a semiconductor substrate. A gate dielectric layer is formed over the p-channel. The gate dielectric layer is doped with a dopant. A first metal gate is formed over the gate dielectric layer.

Abstract: A semiconductor device includes an insulating layer on a substrate, a channel region on the insulating layer, a gate structure on the insulating layer, the gate structure crossing the channel region, source/drain regions on the insulating layer, the source/drain regions being spaced apart from each other with the gate structure interposed therebetween, the channel region connecting the source/drain regions to each other, and contact plugs connected to the source/drain regions, respectively. The channel region includes a plurality of semiconductor patterns that are vertically spaced apart from each other on the insulating layer, the insulating layer includes first recess regions that are adjacent to the source/drain regions, respectively, and the contact plugs include lower portions provided into the first recess regions, respectively.

Abstract: A memory device includes first and second peripheral regions in which peripheral circuits related to data input/output are disposed, a normal cell region which is disposed on the first peripheral region, and in which a plurality of memory cells storing data are formed, and a dummy cell region which is disposed on the second peripheral region, and in which a plurality of dummy cells forming a plurality of capacitors are formed.

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate, forming a gate structure on the substrate, forming a hard mask on the substrate and the gate structure, patterning the hard mask to form trenches exposing part of the substrate, and forming raised epitaxial layers in the trenches. Preferably, the gate structure is extended along a first direction on the substrate and the raised epitaxial layers are elongated along a second direction adjacent to two sides of the gate structure.

Abstract: According to some embodiments, an integrated circuit device is disclosed. The integrated circuit device include at least one inductor having at least one turn, a magnetic coupling ring positioned adjacent to the at least one inductor, the magnetic coupling ring comprising at least two magnetic coupling turns, the at least two magnetic coupling turns are disposed adjacent to the at least one turn to enable magnetic coupling between the at least two magnetic coupling turns and the at least one turn. The integrated circuit device also includes a power electrode and a ground electrode, wherein the power electrode and the ground electrode are coupled to the at least one inductor and the magnetic coupling ring to provide a first current in the at least one inductor having a direction opposite to a second current in the magnetic coupling ring to cancel at least a portion of a magnetic field generated by the at least one inductor.

Abstract: Exemplary semiconductor processing systems may include a processing chamber, and may include a remote plasma unit coupled with the processing chamber. Exemplary systems may also include a mixing manifold coupled between the remote plasma unit and the processing chamber. The mixing manifold may be characterized by a first end and a second end opposite the first end, and may be coupled with the processing chamber at the second end. The mixing manifold may define a central channel through the mixing manifold, and may define a port along an exterior of the mixing manifold. The port may be fluidly coupled with a first trench defined within the first end of the mixing manifold. The first trench may be characterized by an inner radius at a first inner sidewall and an outer radius, and the first trench may provide fluid access to the central channel through the first inner sidewall.