Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure including a programmable logic device, an array of static random-access memory (SRAM) cells, and a first bonding layer including a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of NAND memory cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

Abstract: The present invention provides a chip carrier structure including: a non-circuit substrate, a plurality of micro heaters, and an adhesive layer. The micro heaters are disposed on the non-circuit substrate. The adhesive layer is disposed on the micro heaters, and a plurality of chips are disposed on the adhesive layer. Thereby, the present invention improves the solder yield of the process by a wafer carrying structure and a wafer carrying device.

Abstract: Semiconductor package structures are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon.

Abstract: A method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. The second redistribution lines are formed using the alignment mark for alignment.

Abstract: The present invention provides a film-shaped firing material 1 including sinterable metal particles 10, and a binder component 20, in which a content of the sinterable metal particles 10 is in a range of 15% to 98% by mass, a content of the binder component 20 is in a range of 2% to 50% by mass, a tensile elasticity of the film-shaped firing material at 60° C. is in a range of 4.0 to 10.0 MPa, and a breaking elongation thereof at 60° C. is 500% or greater; and a film-shaped firing material with a support sheet including the film-shaped firing material 1 which contains sinterable metal particles and a binder component, and a support sheet 2 which is provided on at least one side of the film-shaped firing material, in which an adhesive force (a2) of the film-shaped firing material to the support sheet is smaller than an adhesive force (a1) of the film-shaped firing material to a semiconductor wafer, the adhesive force (a1) is 0.1 N/25 mm or greater, and the adhesive force (a2) is in a range of 0.1 N/25 mm to 0.

Abstract: After a MISFET is formed on a substrate including a semiconductor substrate, an insulating layer and a semiconductor layer, an interlayer insulating film and a first insulating film are formed on the substrate. Also, after an opening is formed in each of the first insulating film and the interlayer insulating film, a second insulating film is formed at each of a bottom portion of the opening and a side surface of the opening and also formed on an upper surface of the first insulating film. Further, each of the second insulating film formed at the bottom portion of the opening and the second insulating film formed on the upper surface of the first insulating film is removed by etching. After that, an inside of the opening is etched under a condition that each of the first insulating film and the second insulating film is less etched than the insulating layer.

Abstract: A semiconductor device includes first and second nanowire structures, first and second annular hafnium oxide layers, first and second annular cap layers, and first and second metal gate electrodes. The first and second nanowire structures are suspended over a substrate and respectively have an n-channel region and a p-channel region. The first and second annular hafnium oxide layers encircle the n-channel region and the p-channel region, respectively. The first and second annular cap layers encircle the first and second annular hafnium oxide layers, respectively. The first and second annular cap layers are made of a same material that is lanthanum oxide, yttrium oxide, or strontium oxide. The first and second metal gate electrodes encircle the first and second annular cap layers, respectively. The first and second metal gate electrodes have a same metal composition.

Abstract: An electronic device includes a substrate, a grid structure, and a plurality of polarizing wires. The grid structure is disposed on the substrate and includes a plurality of apertures. The polarizing wires are disposed on the substrate and extend across the apertures. A first number of a portion of the polarizing wires within a first aperture of the apertures is in a range from 50 to 15000.

Abstract: Embodiments of the present disclosure describe techniques for fabricating a stacked integrated circuit (IC) device. A first wafer that includes a plurality of first IC dies may be sorted to identify first known good dies of the plurality of first IC dies. The first wafer may be diced to singulate the first IC dies. A second wafer that includes a plurality of second IC dies may be sorted to identify second know good dies of the plurality of second IC dies. The first known good dies may be bonded to respective second known good dies of the second wafer. In some embodiments, the first known good dies may be thinned after bonding the first know good dies to the second wafer. Other embodiments may be described and/or claimed.

Abstract: A process for fabricating an integrated circuit is provided, including steps of providing a substrate including a silicon layer, a layer of insulator a layer of hard mask and accesses to first and second regions of the silicon layer; forming first and second deposits of SiGe alloy on the first and the second regions in order to form first and second stacks; then protecting the first deposit and maintaining an access to the second deposit; then performing an etch in order to form trenches between the hard mask and two opposite edges of the second stack; then forming a tensilely strained silicon layer in the second region via amorphization of the second region; then crystallization; and enriching the first region in germanium by diffusion from the first deposit.

Abstract: A display panel includes an insulating substrate in which at least one hole is defined, wherein the insulating substrate comprises a hole area in which the hole is defined, a display area surrounding the hole area, and a peripheral area adjacent to the display area, a plurality of pixels in the display area, a plurality of main signal lines in the display area and electrically connected to the pixels, and a plurality of sub-signal lines in the hole area and electrically connected to the pixels, wherein the hole area comprises a line area which surrounds the hole and in which the sub-signal lines are located, and a compensation area between the line area and the display area in a plan view and configured to display a black color.

Abstract: A wafer processing method for processing a wafer with devices formed in regions on a side of a front surface of the wafer, the regions being defined by first scheduled division lines and second scheduled division lines includes a first modified layer forming step and a second modified layer forming step. In the first modified layer forming step, a laser beam is irradiated with its focal point set at a height leveled with a height of a first region located inside the wafer on the side of the front surface of the wafer, whereby first modified layers are formed. In the second modified layer forming step, the laser beam is irradiated with its focal point set at a height leveled with a height of a second region located inside the wafer on a side of a back surface of the wafer, whereby second modified layers are formed.

Abstract: The present technology relates to a solid-state imaging device and an electronic device capable of improving a saturation characteristic. A photo diode is formed on a substrate, and a floating diffusion accumulates a signal charge read from the photo diode. A plurality of vertical gate electrodes is formed from a surface of the substrate in a depth direction in a region between the photo diode and the floating diffusion, and an overflow path is formed in a region interposed between a plurality of vertical gate electrodes. The present technology may be applied to a CMOS image sensor.

Abstract: A first anisotropic conductive film 1A or a second anisotropic conductive film 1B has a first insulating resin layer 2 and a second insulating resin layer 3. The first insulating resin layer 2 is formed of a photopolymerized resin, and the second insulating resin layer 3 is formed of a polymerizable resin. Conductive particles 10 are disposed in a single layer on a surface of the first insulating resin layer 2 on a side of the second insulating resin layer 3. The first anisotropic conductive film further has a third insulating resin layer 4 formed of a polymerizable resin, and the second anisotropic conductive film 1B has an intermediate insulating resin layer 6. The intermediate insulating resin layer 6 is formed of a resin containing no polymerization initiator, and is in contact with the conductive particles 10. These anisotropic conductive films have favorable connection reliability.

Abstract: A manufacturing method of chips from a workpiece including plural planned dividing lines on a front surface includes a cutting step of causing a cutting blade to cut into the workpiece for which a side of the front surface of the workpiece is held by a holding table in such a manner that a side of a back surface of the workpiece is exposed and forming a cut groove that does not reach the front surface of the workpiece on the side of the back surface of the workpiece along each planned dividing line, a sticking step of sticking an expanding sheet to the workpiece, and a dividing step of dividing the workpiece along each planned dividing line by expanding the expanding sheet to form the chips from the workpiece after the sticking step and the cutting step.

Abstract: A substrate oxidation assembly includes: a chamber body defining a processing volume; a substrate support disposed in the processing volume; a plasma source coupled to the processing volume; a steam source fluidly coupled to the processing volume; and a substrate heater. A method of processing a semiconductor substrate includes: initiating conformal radical oxidation of high aspect ratio structures of the substrate comprising: heating the substrate; and exposing the substrate to steam; and conformally oxidizing the substrate. A semiconductor device includes a silicon and nitrogen containing layer; a feature formed in the silicon and nitrogen containing layer having an aspect ratio of at least 40:1; and an oxide layer on the face of the feature having a thickness in a bottom region of the silicon and nitrogen containing layer that is at least 95% of a thickness of the oxide layer in a top region.

Abstract: A semiconductor device of the embodiment includes first and second conductive layer; a silicon nitride layer between the first conductive layer and the second conductive layer; a silicon oxide layer between the silicon nitride layer and the second conductive layer; a silicon oxynitride layer between the silicon oxide layer and the second conductive layer; and a third conductive layer between the first conductive layer and the second conductive layer, the third conductive layer electrically connected to the first and second conductive layer, a first tilt angle of a plane where the third conductive layer is in contact with the silicon oxynitride layer with respect to an interface between the silicon nitride layer and the silicon oxide layer is smaller than a second tilt angle of a plane where the third conductive layer is in contact with the silicon oxide layer with respect to the interface.

Abstract: Electronics devices, having vertical and lateral redistribution interconnects, are disclosed. An electronics device comprises an electronics component (e.g., die, substrate, integrated device, etc.), a die(s), and a separately formed redistribution connection layer electrically coupling the die(s) to the electronics component. The redistribution connection layer comprises dielectric layers on either side of at least one redistribution layer. The dielectric layers comprise openings that expose contact pads of the at least one redistribution layer for electrically coupling die(s) and components to each other via the redistribution connection layer. The redistribution connection layer is flexible and wrap/folded around side edges of die(s) to minimize vertical vias. Various devices and associated processes are provided.

Abstract: In one example, an electroplating system comprises a bath reservoir, a holding device, an anode, a direct current power supply, and a controller. The bath reservoir contains an electrolyte solution. The holding device holds a wafer submerged in the electrolyte solution. The wafer comprises features covered by a cobalt layer. The anode is opposite to the wafer and submerged in the electrolyte solution. The direct current power supply generates a direct current between the holding device and the anode. A combination of forward and reverse pulses is applied between the holding device and the anode to electroplate a copper layer on the cobalt layer of the wafer.

Abstract: A display device may include a substrate, a thin film transistor, a first electrode, a second electrode, and a barrier. The thin film transistor is disposed on the substrate. The first electrode is electrically connected to the thin film transistor. The second electrode overlaps the first electrode. The barrier has a first portion and a second portion. The second portion is disposed between the first portion and the second electrode and is fluorine-doped. A side surface of the first portion is part of a boundary of an opening of the barrier and is hydrophilic. The opening of the barrier is disposed between the first electrode and the second electrode.