Abstract: A first anisotropic conductive film 1A or a second anisotropic conductive film 1B has a first insulating resin layer 2 and a second insulating resin layer 3. The first insulating resin layer 2 is formed of a photopolymerized resin, and the second insulating resin layer 3 is formed of a polymerizable resin. Conductive particles 10 are disposed in a single layer on a surface of the first insulating resin layer 2 on a side of the second insulating resin layer 3. The first anisotropic conductive film further has a third insulating resin layer 4 formed of a polymerizable resin, and the second anisotropic conductive film 1B has an intermediate insulating resin layer 6. The intermediate insulating resin layer 6 is formed of a resin containing no polymerization initiator, and is in contact with the conductive particles 10. These anisotropic conductive films have favorable connection reliability.

Abstract: The present technology relates to a solid-state imaging device and an electronic device capable of improving a saturation characteristic. A photo diode is formed on a substrate, and a floating diffusion accumulates a signal charge read from the photo diode. A plurality of vertical gate electrodes is formed from a surface of the substrate in a depth direction in a region between the photo diode and the floating diffusion, and an overflow path is formed in a region interposed between a plurality of vertical gate electrodes. The present technology may be applied to a CMOS image sensor.

Abstract: A wafer processing method for processing a wafer with devices formed in regions on a side of a front surface of the wafer, the regions being defined by first scheduled division lines and second scheduled division lines includes a first modified layer forming step and a second modified layer forming step. In the first modified layer forming step, a laser beam is irradiated with its focal point set at a height leveled with a height of a first region located inside the wafer on the side of the front surface of the wafer, whereby first modified layers are formed. In the second modified layer forming step, the laser beam is irradiated with its focal point set at a height leveled with a height of a second region located inside the wafer on a side of a back surface of the wafer, whereby second modified layers are formed.

Abstract: A substrate oxidation assembly includes: a chamber body defining a processing volume; a substrate support disposed in the processing volume; a plasma source coupled to the processing volume; a steam source fluidly coupled to the processing volume; and a substrate heater. A method of processing a semiconductor substrate includes: initiating conformal radical oxidation of high aspect ratio structures of the substrate comprising: heating the substrate; and exposing the substrate to steam; and conformally oxidizing the substrate. A semiconductor device includes a silicon and nitrogen containing layer; a feature formed in the silicon and nitrogen containing layer having an aspect ratio of at least 40:1; and an oxide layer on the face of the feature having a thickness in a bottom region of the silicon and nitrogen containing layer that is at least 95% of a thickness of the oxide layer in a top region.

Abstract: A manufacturing method of chips from a workpiece including plural planned dividing lines on a front surface includes a cutting step of causing a cutting blade to cut into the workpiece for which a side of the front surface of the workpiece is held by a holding table in such a manner that a side of a back surface of the workpiece is exposed and forming a cut groove that does not reach the front surface of the workpiece on the side of the back surface of the workpiece along each planned dividing line, a sticking step of sticking an expanding sheet to the workpiece, and a dividing step of dividing the workpiece along each planned dividing line by expanding the expanding sheet to form the chips from the workpiece after the sticking step and the cutting step.

Abstract: A semiconductor device of the embodiment includes first and second conductive layer; a silicon nitride layer between the first conductive layer and the second conductive layer; a silicon oxide layer between the silicon nitride layer and the second conductive layer; a silicon oxynitride layer between the silicon oxide layer and the second conductive layer; and a third conductive layer between the first conductive layer and the second conductive layer, the third conductive layer electrically connected to the first and second conductive layer, a first tilt angle of a plane where the third conductive layer is in contact with the silicon oxynitride layer with respect to an interface between the silicon nitride layer and the silicon oxide layer is smaller than a second tilt angle of a plane where the third conductive layer is in contact with the silicon oxide layer with respect to the interface.

Abstract: Electronics devices, having vertical and lateral redistribution interconnects, are disclosed. An electronics device comprises an electronics component (e.g., die, substrate, integrated device, etc.), a die(s), and a separately formed redistribution connection layer electrically coupling the die(s) to the electronics component. The redistribution connection layer comprises dielectric layers on either side of at least one redistribution layer. The dielectric layers comprise openings that expose contact pads of the at least one redistribution layer for electrically coupling die(s) and components to each other via the redistribution connection layer. The redistribution connection layer is flexible and wrap/folded around side edges of die(s) to minimize vertical vias. Various devices and associated processes are provided.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening extending through the alternating sack, and a memory opening fill structure located within the memory opening. The memory opening fill structure includes a pedestal channel portion, a memory film overlying the pedestal channel portion, a vertical semiconductor channel located inside the memory film, and a channel connection strap that extends through an opening of the memory film and contacting the pedestal channel portion and the vertical semiconductor channel. The channel connection strap has a topmost surface located below a horizontal plane including a top surface of the vertical semiconductor channel.

Abstract: A display device may include a substrate, a thin film transistor, a first electrode, a second electrode, and a barrier. The thin film transistor is disposed on the substrate. The first electrode is electrically connected to the thin film transistor. The second electrode overlaps the first electrode. The barrier has a first portion and a second portion. The second portion is disposed between the first portion and the second electrode and is fluorine-doped. A side surface of the first portion is part of a boundary of an opening of the barrier and is hydrophilic. The opening of the barrier is disposed between the first electrode and the second electrode.

Abstract: In one example, an electroplating system comprises a bath reservoir, a holding device, an anode, a direct current power supply, and a controller. The bath reservoir contains an electrolyte solution. The holding device holds a wafer submerged in the electrolyte solution. The wafer comprises features covered by a cobalt layer. The anode is opposite to the wafer and submerged in the electrolyte solution. The direct current power supply generates a direct current between the holding device and the anode. A combination of forward and reverse pulses is applied between the holding device and the anode to electroplate a copper layer on the cobalt layer of the wafer.

Abstract: A light-emitting component a first layer stack configured to generate light, at least one additional layer stack configured to generate light, where each of the first layer stack and the at least one additional layer stack are separately drivable from one another and where an auxiliary structure is arranged between the first layer stacks and the at least one additional layer stacks.

Abstract: A dual mode snap back circuit device is disclosed. The dual mode snap back device may be used for electrostatic discharge (ESD) protection, and may provide both positive ESD protection and negative ESD protection. The dual mode snap back device may implement both an n-type metal-oxide-semiconductor (NMOS) transistor (e.g., a gate-grounded NMOS transistor, such as a gate-grounded extended drain NMOS (GGEDNMOS) transistor) to provide protection against positive ESD events and a bipolar junction transistor (BJT) (e.g., a PNP BJT) to provide protection against negative ESD events. Other embodiments may be described and claimed.

Abstract: A method for forming a photovoltaic device includes forming a doped layer on a crystalline substrate, the doped layer having an opposite dopant conductivity as the substrate. A non-crystalline transparent conductive electrode (TCE) layer is formed on the doped layer at a temperature less than 150 degrees Celsius. The TCE layer is flash annealed to crystallize material of the TCE layer at a temperature above about 150 degrees Celsius for less than 10 seconds.

Abstract: A device for detecting a chemical species, including a Geiger-mode avalanche diode, which includes a body of semiconductor material delimited by a front surface. The semiconductor body includes: a cathode region having a first type of conductivity, which forms the front surface; and an anode region having a second type of conductivity, which extends in the cathode region starting from the front surface. The detection device further includes: a sensitive structure arranged on the anode region and including at least one sensitive region, which has an electrical permittivity that depends upon the concentration of the chemical species; and a resistive region, arranged on the sensitive structure and electrically coupled to the anode region.

Abstract: Anisotropic conductive film produced that a light-transmitting transfer die having openings with conductive particles disposed therein is prepared, and photopolymerizable insulating resin squeezed into openings to transfer conductive particles onto the surface of the photopolymerizable insulating resin layer, first connection layer is formed which has a structure in which conductive particles are arranged in a single layer in a plane direction of photopolymerizable insulating resin layer and the thickness of photopolymerizable insulating resin layer in central regions between adjacent ones of the conductive particles is smaller than thickness of photopolymerizable insulating resin layer in regions in proximity to conductive particles; first connection layer is irradiated with ultraviolet rays through light-transmitting transfer die; release film is removed from first connection layer; second connection layer is formed on the surface of first connection layer opposite to light-transmitting transfer die; and th

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. At least one dielectric material portion is formed over the substrate adjacent to the alternating stack. Memory stack structures are formed through the alternating stack. A trench extending through the alternating stack and a via cavity extending through the at least one dielectric material portion are formed using a same anisotropic etch process. The via cavity is deeper than the trench and the via cavity extends into an upper portion of the substrate. The sacrificial material layers are replaced with electrically conductive layers using the trench as a conduit for an etchant and a reactant. A trench fill structure is formed in the trench, and a via structure assembly is formed in the via cavity using simultaneous deposition of material portions. A bonding pad may be formed on the bottom surface of the via structure assembly.

Abstract: Methods related to the treatment of a quantum computing device to increase channel mobility are described. An example method includes forming a superconducting metal layer on a surface of a wafer. The method further includes selectively removing a portion of the superconducting metal layer to allow a subsequent formation of a gate dielectric associated with the device, where the selectively removing causes a decrease in channel mobility associated with the quantum computing device. The method further includes prior to forming the gate dielectric, subjecting the wafer to a plasma treatment, where a set of parameters associated with the plasma treatment is selected to increase the channel mobility.

Abstract: An electro-optical device includes a contact hole configured to electrically connect a scanning line and a gate electrode of a TFT as a transistor, the contact hole being provided, in plan view, along a semiconductor layer of the TFT and including a body portion spaced apart from a channel region of the semiconductor layer by a first distance, and a protruded portion protruding from the body portion toward a region other than the channel region of the semiconductor layer, and spaced apart from the region other than the channel region by a second distance, which is less than the first distance.

Abstract: A semiconductor device, and a method of manufacturing a semiconductor device, includes first stack structures enclosing first channel structures and spaced apart from each other. The first channel structures are spaced apart from each other at a first distance in each of the first stack structures and the first stack structures are spaced apart from each other at a second distance.

Abstract: An organic light emitting diode (OLED) display panel and manufacturing method thereof are provided. The display panel includes a substrate, a thin film transistor layer, and a light emitting structure, wherein the thin film transistor layer includes a polysilicon layer, a gate dielectric layer positioned on the polysilicon layer, a gate metal layer positioned on the gate dielectric layer, a gate buffer layer positioned on the gate dielectric layer, and an interlayer dielectric layer covering the gate dielectric layer, the gate metal layer, and the gate buffer layer.