Abstract: A liquid-crystal display device of optical writing type includes a first transparent substrate, a first transparent electrode layer formed on the first transparent substrate, a photoconductive layer formed on the first transparent electrode layer, a light-absorbing layer composed of an organic film, the light-absorbing layer formed on the photoconductive layer, a dielectric layer formed on the light-absorbing layer, a second transparent substrate, a second transparent electrode layer formed on the second transparent substrate, and a liquid-crystal layer disposed between the second transparent electrode layer and the dielectric layer.

Abstract: A color display device capable of emitting three primary colors of equalized luminance, so that color display of high quality which is free of unevenness may be accomplished. The color display device is so constructed that a fluorescent display section including first and second luminous sections different in luminous characteristics is combined with an optical rotation section and color polarizing plates. The fluorescent display section and optical rotation section are synchronously driven.

Abstract: An active matrix liquid crystal display panel is composed of a number of liquid crystal display elements arranged in the form a matrix, each of the liquid crystal display elements being composed of an individual display electrode, a common electrode, and a liquid crystal material sandwiched between the individual display electrode and the common electrode. The individual display electrode of each of the liquid crystal display elements is selectively activated through an associated active element. A liquid crystal display element connected to a defective active element is modified by burning the associated color filter and/or heating the liquid crystal to render the liquid crystal translucent to become a half tone display element, so that the liquid crystal display element connected to the defective active element becomes overshadowed or inconspicuous when the display panel is in operation.

Abstract: An uninterrupted event-time recorder enables high-precision measurements of the time-of-occurrence of randomly- and rapidly-occurring, digitally specified events such as the leading and/or trailing edges of asynchronous pulses. The lowest order binary digits of the recorder are constructed of high-speed synchronous integrated circuit counter devices. For an N-bit timer having M low-order bits, the highest order (N-M) bit counting is executed by two parallel (N-M)-bit slow-speed counters, one of which is incremented by the terminal count of the M-bit high-speed counter and the other which is incremented by the most significant bit (MSb) of the M-bit counter. The (N-M)-bit counters are read out through a multiplexer controlled by the MSb.

Abstract: Disclosed herein is an MIM device having a hard carbon film as the insulator. The hard carbon film contains at least one of the following elements: a group III element, a group IV element, a group V element, an alkali metal element, an alkaline earth metal element, nitrogen, oxygen, a chalcogen element or a halogen element.

Abstract: Disclosed is a color liquid crystal display device having a plurality of pixels, in which conductive films are arranged at regions corresponding to the respective pixels, a light-shielding conductive layer is connected to the conductive films and extends in a region between the pixels, and color filters are formed on the conductive films.

Abstract: An electro-optical liquid crystal display device includes at least one of the optically anisotropic layers has three main refractive indices N1o, N2o and N3e. The axis corresponding to N3e is in the direction approximately parallel to the surfaces of the substrates of the liquid crystal cell and N3e is smaller than N1o and N2o. The device may include a homogenous or twisted liquid crystall cell with the cell and anisotropic layer sandwiched between two polarizers.

Abstract: The generator of drive signals comprises a ramp generator suitable for receiving a square waveform input signal and for converting it into an output signal variable between a lower level and an upper level with upward and downward ramps having a preset slope, a first comparator with a non-inverting input connected to the output of said ramp generator and an inverting input connected to a first reference signal source and a second comparator with an inverting input connected to the output of said ramp generator and a non-inverting input connected to a second reference signal source.

Abstract: Electric charge transmit elements (QD) transmit electric charge from a terminal side (NA) to a control electrode side (NB) of the circuit. The voltage at the control electrode side (NB) is raised by a capacitor configuration (CB). Voltage stabilizing elements (QC) are connected in parallel to the electric charge transmit elements between the terminal side and the control electrode side. In transferring the electric charge from the control electrode side (NB) to the other terminal side (NC), the voltage at the control electrode side (NB) is kept higher than the other terminal side (NC). Therefore, because loss of voltage by the electric charge transfer elements (QB) in transferring the electric charge is eliminated, a predetermined voltage is obtained efficiently in a short time, and a highly reliable booster circuit is provided.

Abstract: A color display medium is constituted by a colored polymer layer having at least two display regions of different colors, typically three colors of blue, green and red, along the extension of the polymer layer. The display regions of different colors have respectively different wavelength regions of light absorption or respectively different temperatures of thermal transition between transparent and scattering states.

Abstract: A master-slave type flip-flop circuit with first and second transmission gates receives an input pulse signal and an inverted input pulse signal at a data input terminal and an inverted data input terminal, respectively, and receives a clock signal at a common clock input terminal. A first data holding section includes first and second inverters and first and second resistors cross-connected between input and output terminals of the first and second inverters for receiving outputs of the first and second transmission gates at the input terminals of the first and second inverters. Third and fourth transmission gates receive outputs of the first and second inverters, respectively, of the data holding section and further receive an inverted clock signal at a common inverted clock input terminal.

Abstract: A liquid crystal light valve, comprising a layer of liquid crystal for storing image information and a photoconductor aligned with the liquid crystal and positioned in closed proximity thereto for effecting an electric field applied across the liquid crystal. Apparatus is provided for simultaneously applying an electric field across the liquid crystal and photoconductor while impinging optical image information on the photoconductor, the photoconductor and applied field combining to produce a modified electric field across the liquid crystal which impresses the image information on the photoconductor into the liquid crystal.

Abstract: A second circuit to which back-up power is supplied, such as a RAM, is connected downstream of a first circuit to which no back-up power is supplied, such as a CPU. A gate circuit inhibits the output signal of the first circuit to the second circuit and provides a predetermined level to the second circuit when the output signal of the first circuit is at an indefinite level and prevents a penetration current from flowing through the second circuit.

Abstract: A high speed, D-type flip-flop is implemented using eight complementary metal-oxide semiconductor (CMOS) tristate inverters. The flip-flop includes both D and D/ data input terminals and parallel data paths from the data input terminals to Q and Q/ output terminals. The improved circuit design realizes higher operating speed than prior CMOS flip-flops by eliminating the inverter delays present in single path flip-flops and providing only two gates in the data paths between the input and output terminals.

Abstract: A delay circuit for producing in an electrical circuit a time delay. The circuit includes a pulse generator which produces an edge at a given time interval after an edge is applied to its input. The time interval can be adjusted so that it automatically follows a reference time interval such as a clock period. The circuit has application in the read circuitry of digital tape devices.

Abstract: Dummy power source wirings connected to a power source wiring are arranged in empty regions among the signal wirings that cross the clock wirings, the dummy power source wirings being arranged over or under the clock wirings in a manner to cross the clock wirings. The dummy power source wirings are formed to equalize the capacitances of the wirings whose lengths should be equalized among, for example, the clock distributing circuits or among the clock drivers.

Abstract: A reflective type liquid crystal display device is achieved with enhanced brightness and contrast ratio utilizing only one polarizing plate or polarizer and a refelctor in combination with a liquid crystal cell wherein the light propagating through the liquid crystal cell to the reflector is substantially of linear polarization. By employing a single polarizer, the effective brightness and contrast of the display can be increased by about 12% and the multi-coloring effect in a monochromatic black/white display can be significantly reduced. To obtain an ideal brightness level, linearly polarized light, which enters the liquid crystal cell through the single polarizer, is required to be transmitted twice through the liquid crystal layer and then passed again through the polarizer under the same conditions as in the case of obtaining linear polarization utilized in the transmissive type mode employing two parallel polarizing plates.

Abstract: An input bias circuit employs a gate input type CCD register and an inversion-type amplifier. An output node of the inversion-type amplifier is connected to the input gate electrode of the CCD register, and an input signal to be biased is supplied to the input gate electrode. An output node of the inversion-type amplifier is connected to the floating diffusion region of the CCD register, and a signal charge is picked up from the floating diffusion region. A comparator performs comparison among the low level of the injection pulse supplied to the input diffusion region (which serves as an input diode), the potential level of the input signal supplied to the input gate electrode of the CCD register, and the level of the low-level generated by a low-level signal generating means. On the basis of this comparison, the potential level of the input signal of the CCD register is controlled such that it is higher than the low level of the injection pulse.

Abstract: An improved sense amplifier driver for sensing and restoring data in memory cells is disclosed. Pull-up means in the form of p-channel MOS transistors are respectively provided for forcibly pulling up the gate voltage of delayable p-channel MOS transistors within the first inverter of the sensing clock driver and the second inverter of the restore clock driver in the trailing transient periods of the sensing and restoring clock signals. The formation of a DC current path between the power line and the ground line in any one of the delayable p-channel MOS transistors is prevented, thereby making it possible to avoid the unnecessary power dissipation. Further, delaying resistances are installed respectively in the first inverter of the sensing clock driver and in the second inverter of the restoring clock driver to make the slope of the leading edges of the sensing and restoring clocks less steep, thereby making it possible to exclude the occurrence of noise.

Abstract: In a driver circuit, two P-channel MOS transistors are connected in parallel between a supply terminal and an output terminal, and two P-channel MOS transistors are connected in parallel between a ground terminal and the output terminal. When a signal of the "H" level is applied to an input terminal, a signal of the "L" level is applied sequentially to these transistors. As a result, the N-channel MOS transistors are sequentially turned off, and thereafter the P-channel MOS transistors are sequentially turned on. When a signal of the "L" level is applied to the input terminal, a signal of the "H" level is applied sequentially to these transistors. As a result, the P-channel MOS transistors are sequentially turned off, and thereafter the N-channel MOS transistors are sequentially turned on.