Patents Examined by Stephen E. Jones
  • Patent number: 11557461
    Abstract: In one embodiment, an RF impedance matching network is disclosed. The matching network is coupled between an RF source having a variable frequency and a plasma chamber having a variable chamber impedance. The matching network includes a variable reactance element (VRE), and a control circuit coupled to the VRE and a sensor, the sensor configured to detect an RF parameter. To cause an impedance match between the RF source and the plasma chamber, the control circuit determines, based on the detected RF parameter and a VRE configuration, a new source frequency for the RF source. The impedance match then causes the variable frequency of the RF source to alter to the new source frequency.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: January 17, 2023
    Inventor: Imran Ahmed Bhutta
  • Patent number: 11552657
    Abstract: The invention relates to a directional coupler comprising a non-straight main conductor line for receiving a high power signal and at least one coupling element. The main conductor line is arranged to run in a plane P0. The at least one coupling element is arranged sectionally parallel to the main conductor line. Further, the invention relates to a method for measuring RF voltage and/or RF power using a directional coupler. The method comprises the steps of combining the measured signals of the directional coupler and the measured voltage and current values of the VI sensor unit. In case, one of the measured signals has a low or zero level the sensitivity of the measuring of RF voltage and/or RF power is increased.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: January 10, 2023
    Assignee: COMET AG PLASMA CONTROL TECHNOLOGIES
    Inventors: Nikolai Schwerg, André Grede
  • Patent number: 11539105
    Abstract: An attenuator is configured to attenuate and phase-shift a radiofrequency signal according to a control signal, having a plurality of first attenuation cells (A1, AN?1), configured to attenuate said radiofrequency signal by a predetermined value and activated according to a particular bit of the control signal, and implementing a combinatorial logic on the bits of the control signal that are used to control the first attenuation cells, and at least one second attenuation cell (B1, BM) configured to attenuate said radiofrequency signal by a predetermined value and activated according to a particular output implementing the combinatorial logic. A control node is also provided for an array antenna having such an attenuator, and an array antenna having an array of such control node and a satellite.
    Type: Grant
    Filed: July 3, 2020
    Date of Patent: December 27, 2022
    Assignee: THALES
    Inventors: Stéphane Rochette, Thierry Adam, Benjamin Therond, Vincent Armengaud
  • Patent number: 11538662
    Abstract: In one embodiment, the present disclosure is directed to a method for impedance matching. A matching network includes first and second reactance elements configured to provide variable positions. A first parameter of the matching network is determined based on a detected value. The method determines first two-port parameters from a first one-dimensional array that corresponds to a first portion of the matching network using the first reactance element position, and second two-port parameters from a second one-dimensional array that corresponds to a second portion of the matching network using the second reactance element position. An output parameter is calculated based on the first parameter, the first two-port parameters, and the second two-port parameters. New first and second reactance element positions are determined from a match position table using the calculated output parameter. The method then alters the reactance elements accordingly to reduce a reflected power.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: December 27, 2022
    Inventor: Michael Gilliam Ulrich
  • Patent number: 11533037
    Abstract: Digital step attenuator (DSA) and digital phase shifter (DPS) multi-stage circuit architectures that provide for high resolution. Embodiments use a dithering approach to weight bit positions to provide a much finer resolution than the lowest-valued individual stage. Bit position weights for stages are determined so as to enable selection of combinations of n bit positions that provide a desired total attenuation or phase shift range while allowing utilization of the large number of states (2n) available to produce fractional intermediate steps of attenuation or phase shift. The fractional intermediate steps have a resolution finer than the lowest-valued stage. Bit position weights may be determined using a weighting function, including weightings determined from a linear series, a geometric series, a harmonic series, or alternating variants of such series. In some embodiments, at least one bit position has a fixed value that is not determined by the bit position weighting function.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: December 20, 2022
    Assignee: pSemi Corporation
    Inventors: Vikas Sharma, Peter Bacon
  • Patent number: 11532862
    Abstract: Apparatuses, methods, and systems for a housing structure for maintaining alignment between ceramic sections of a bandpass filter are disclosed. One housing structure includes an L-shaped outer structure, a plurality of flexure portions, wherein at least one of flexure portion extends from an end portion of each of extended arms of the L-shaped outer structure, wherein each flexure portion extends inward perpendicular to each of the extended end portion, and a plurality of reference datums, wherein at least one reference datum is located between an L-joint of the L-shaped outer structure, and a one of the flexure portions. The housing structure operates to receive a plurality of sections of a waveguide filter, wherein each section includes a plurality of planar surfaces, wherein the datums and the flexure portions are operative to maintain alignment of the sections of the waveguide filter relative to each other.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: December 20, 2022
    Assignee: Meta Platforms, Inc.
    Inventors: Farbod Tabatabai, Haris Alijagic
  • Patent number: 11532863
    Abstract: A broadband microstrip ferrite circulator or isolator includes a carrier. The broadband microstrip ferrite circulator or isolator further includes a dielectric substrate having an opening therein. The broadband microstrip ferrite circulator or isolator further includes a ferrite disc positioned within the opening of the dielectric substrate. The broadband microstrip ferrite circulator or isolator further includes a conductor having three contacts extending therefrom, the conductor being positioned on the ferrite disc. The broadband microstrip ferrite circulator or isolator further includes a magnet. The broadband microstrip ferrite circulator or isolator further includes a spacer positioned between the conductor and the magnet.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: December 20, 2022
    Inventors: David E. Barry, James P. Kingston
  • Patent number: 11522524
    Abstract: A programmable voltage variable attenuator (VVA) that enables selection among multiple analog, continuous attenuation ranges. Some embodiments include a dual-mode interface to enable digitally programming a DAC and provide the analog output to control the attenuation level of the VVA, or alternatively apply an externally provided analog voltage to directly control the VVA attenuation level. A VVA may be used in conjunction with a digital step attenuator (DSA). Some embodiments include circuitry for changing the VVA reference impedance. The attenuator architecture of the VVA includes one or more variable resistance shunt elements and/or series elements which may be a resistor and FET circuit controlled by a provided variable analog voltage. The multiple resistance element architecture may be implemented with stacked FET devices. Embodiments for the VVA may be based, for example, on T-type, Bridged-T type, Pi-type, L-pad type, reflection type, or balanced coupler type attenuators.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: December 6, 2022
    Assignee: pSemi Corporation
    Inventor: Peter Bacon
  • Patent number: 11521833
    Abstract: In one embodiment, a method of matching an impedance is disclosed. An impedance matching network is coupled between a radio frequency (RF) source and a plasma chamber. The matching network includes a variable reactance element (VRE) having different positions for providing different reactances. The RF source has an RF source control circuit carrying out a power control scheme to control a power delivered to the matching network. Based on a determined parameter, a new position for the VRE is determined to reduce a reflected power at the RF input of the matching network. The matching network provides a notice signal to the RF source indicating the VRE will be altered. In response to the notice signal, the RF source control circuit alters the power control scheme. While the power control scheme is altered, the VRE is altered to the new position.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: December 6, 2022
    Inventor: Imran Ahmed Bhutta
  • Patent number: 11522261
    Abstract: A multi-mode transmission line includes a first and second conductive layers, first and second waveguide walls, a strip line, and a blind conductor. The second conductive layer that is formed over the first conductive layer. The first waveguide wall is elongated in a first direction and is in contact with the first conductive layer and the second conductive layer in a vertical direction. The second waveguide wall is elongated in the first direction parallel to the first waveguide wall and is in contact with the first conductive layer and the second conductive layer in the vertical direction. The strip line is formed between the first and second conductive layers and between the first and second waveguide walls. The blind conductor is connected to one of the first conductive layer, the second conductive layer, the first waveguide wall, or the second waveguide wall.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: December 6, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jindo Byun, Seonkyoo Lee, Hyunjin Kim
  • Patent number: 11522260
    Abstract: The present invention relates to a cavity filter and, in particular, provides an advantage of preventing performance deterioration of an antenna device by efficiently absorbing an assembly tolerance which may occur due to assembly design and preventing an interruption of an electrical flow, by comprising: an RF signal connecting part provided to be spaced apart at a predetermined distance from an external member having an electrode pad formed on one surface thereof; a terminal part which electrically connects the electrode pad of the external member to the RF signal connecting part, while absorbing an assembly tolerance existing within the predetermined distance and simultaneously preventing an interruption of an electrical flow between the electrode pad and the RF signal connecting part; a dielectric body which is inserted into a terminal insertion hole so as to surround the outside of the terminal part; and an elastic member which has a portion of the edge supported by the dielectric body and which elastica
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: December 6, 2022
    Assignee: KMW INC.
    Inventors: Joung Hoe Kim, Sang Yoong Kim
  • Patent number: 11509030
    Abstract: This application provides an example dielectric filter and an example communications device. The dielectric filter includes a dielectric block. At least two resonant through holes that are parallel to each other are provided in the dielectric block. The resonant through hole is a stepped hole. The stepped hole includes a large stepped hole and a small stepped hole that are arranged coaxially and that are in communication. The small stepped hole passes through a first surface of the dielectric block. The large stepped hole passes through a second surface of the dielectric block. A stepped surface is formed between the large stepped hole and the small stepped hole. The surfaces of the dielectric block are covered with conductor layers. The conductor layers cover the surfaces of the dielectric block and inner walls of the large stepped hole and the small stepped hole. A conductor layer of the inner wall of the large stepped hole is short-circuited with a conductor layer of the second surface.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: November 22, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Xiaofeng Zhang, Dan Liang, Zheng Cui
  • Patent number: 11509029
    Abstract: A dielectric waveguide filter comprising a block of dielectric material including exterior surfaces covered with a layer of conductive material. A plurality of resonators are formed on the block. RF signal input/outputs are formed on the block. An RF signal is transmitted through the block in a serpentine pattern. In one embodiment, a RF signal transmission channel is formed in the block and extends between and surrounding selected ones of the plurality of resonators in a serpentine pattern. In one embodiment, selected ones of the plurality of resonators are comprised of respective islands of dielectric material formed on one of the top and bottom surfaces of the block of dielectric material surrounded by the channel and respective counter-bores formed and extending into the respective islands of dielectric material. In another embodiment, the respective islands of dielectric material and counter-bores defining the respective resonators are formed in opposed top and bottom surfaces of the block.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: November 22, 2022
    Assignee: CTS Corporation
    Inventor: Dong Jing
  • Patent number: 11490950
    Abstract: A combined isolator-diplexer device for supplying radiofrequency (RF) energy and microwave energy obtained from separate sources to a probe via a common signal pathway. The invention combines into a single unit all the necessary components to isolate a microwave channel from an RF channel whilst providing a high withstanding voltage (e.g. greater than 10 kV). The device comprises a waveguide isolator for isolating the microwave channel having a pair of DC isolation barriers arranged therein to provide a pair of series-connected capacitive structures between a ground conductor at an output of the combining circuit and a conductive input section of the waveguide isolator.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: November 8, 2022
    Assignee: CREO MEDICAL LIMITED
    Inventors: Christopher Paul Hancock, Malcolm White
  • Patent number: 11495870
    Abstract: The present invention relates to a cavity filter and a connecting structure included therein. The cavity filter includes: an RF signal connecting portion spaced apart, by a predetermined distance, from an outer member having an electrode pad provided on a surface thereof; and a terminal portion configured to electrically connect the electrode pad of the outer member and the RF signal connecting portion so as to absorb assembly tolerance existing at the predetermined distance and to prevent disconnection of the electric flow between the electrode pad and the RF signal connecting portion, wherein the terminal portion includes: a first side terminal contacted with the electrode pad; and a second side terminal having a housing space in which a part of the first side terminal is housed, and connected to the RF signal connecting portion, wherein the first side terminal is provided as an elastic deformable body whose part is radially widened or narrowed against an assembly force provided by an assembler.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: November 8, 2022
    Assignee: KMW INC.
    Inventors: Nam Shin Park, Joung Hoe Kim, Sung Ho Jang
  • Patent number: 11489244
    Abstract: The invention relates to the field of microwave engineering, and in particular, to waveguide-type coupling devices consisting of two coupled lines. The invention can be utilized as a hardware component for thin-film integrated high-frequency units (such as splitter/adder circuits), UHF power amplifiers, couplers, radiofrequency multiplexers, phase shifters, filters and other units in wireless devices used for various purposes. The benefit of the invention claimed lies in increase in efficiency of utilization of the usable area of a dielectric substrate and decrease in overall dimensions of the device and widening of the operating frequency band. This benefit is achieved by inclusion of two electromagnetically coupled microstrip transmission lines to the helical ultra-wideband microstrip quadrature directional coupler, which are designed as flat bilifar helices and are arranged on a dielectric substrate, the backside of which is partially or completely metalized or suspended over a metal surface.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: November 1, 2022
    Assignee: AKCIONERNOE OBSHESTVO MICROVOLNOVYE SISTEMY
    Inventors: Aleksey Vladimirovich Radchenko, Vladimir Vasilievich Radchenko
  • Patent number: 11486900
    Abstract: A probe apparatus of a millimeter or submillimeter radio frequency band comprises transition layers having outermost layers on opposite surfaces of the probe apparatus. An internal transition cavity extends through the transition layers for guiding electromagnetic radiation within the probe apparatus. A probe layer disposed between the transition layers, the probe layer having a lateral transmission line for interacting with the electromagnetic radiation guided by the internal transmission cavity.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: November 1, 2022
    Assignee: TEKNOLOGIAN TUTKIMUSKESKUS VTT OY
    Inventors: Vladimir Ermolov, Antti Lamminen, Jussi Säily, Tauno Vähä-Heikkilä, Pekka Rantakari
  • Patent number: 11489243
    Abstract: A dielectric having a first main surface and a second main surface facing each other, a main line provided on a side of the first main surface in contact with the dielectric, and a sub line provided on the side of the first main surface in contact with the dielectric are included, the dielectric has a first portion in contact with the main line and a second portion in contact with the sub line, and when the first main surface is viewed in a plan view, between the first portion and the second portion, a third portion having a relative dielectric constant changing along a direction intersecting with the main line and the sub line is located.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: November 1, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Ryangsu Kim
  • Patent number: 11476813
    Abstract: A receiver front end (300) having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch (235) is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch (260) is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the gm of the input stage of the amplifier, thus improving the noise figure of the amplifier.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: October 18, 2022
    Assignee: pSemi Corporation
    Inventors: Miles Sanner, Emre Ayranci
  • Patent number: 11476554
    Abstract: Embodiments of the invention include dielectric waveguides and connectors for dielectric waveguides. In an embodiment a dielectric waveguide connector may include an outer ring and one or more posts extending from the outer ring towards the center of the outer ring. In some embodiments, a first dielectric waveguide secured within the dielectric ring by the one or more posts. In another embodiment, an enclosure surrounding electronic components may include an enclosure wall having an interior surface and an exterior surface and a dielectric waveguide embedded within the enclosure wall. In an embodiment, a first end of the dielectric waveguide is substantially coplanar with the interior surface of the enclosure wall and a second end of the dielectric waveguide is substantially coplanar with the exterior surface of the enclosure wall.
    Type: Grant
    Filed: July 1, 2017
    Date of Patent: October 18, 2022
    Assignee: Intel Corporation
    Inventors: Georgios Dogiamis, Sasha Oster, Telesphor Kamgaing, Erich Ewy, Adel Elsherbini, Johanna Swan