Abstract: An optical storage medium recording apparatus is provided a data preparing and ECC encoding circuit that both prepares the data by combining different categories of data into data sequences in accordance with a data layout on the optical storage medium and encodes the combined data. The encoded data is temporarily stored in a data buffer, and subsequently successively read out by a recording circuit for recording onto the optical storage medium according to the data layout. For a Blu-ray disc recording apparatus, the data preparing and ECC encoding circuit includes a LDC/BIS encoder for generating long distance error correction codes (LDC) and burst indicator subcodes (BIS) from the combined data to form LDC and BIS encoded data, which is temporarily stored in the data buffer. The recording circuit includes an interleave circuit for interleaving the LDC and BIS data to form physical clusters for recording on the disc.

Abstract: Various systems and methods for generating and/or ordering error indications are disclosed herein. In some cases, the error indication is used as an erasure pointer in a memory access system. As one particular example, a system for ordering erasure pointers is disclosed that includes a group of N sort cells, where N is a whole number. Each of the sort cells is operable to maintain a respective error indication that includes an error value and an associated error pointer. Further, the group of N sort cells is operable to receive an incoming error indication including error value and associated error pointer, and to update the error indication of one or more of the group of N sort cells based in part on the incoming error value. The system also includes a selector circuit that is operable to allow selectable access to each of the respective error pointers maintained in the group of N sort cells.

Abstract: A method, system, and computer software product for operating a collection of memory cells. Memory cells are organized into a group of memory cells, with each memory cell storing a binary multi-bit value delimited by characteristic parameter bands. Two adjacent characteristic parameter bands are assigned binary multi-bit values that differ by only one bit. In one embodiment, an error correction unit calculates an actual parity check value of the retrieved binary multi-bit values for the group of memory cells. If the actual parity check value is not equal to the expected parity check value, the error correction unit assigns the error memory cell a corrected binary multi-bit value with the characteristic parameter value within the characteristic parameter band adjacent to the characteristic parameter band associated with the retrieved binary multi-bit value such that calculating a second actual parity check value correctly indicates the parity for the group of memory cells.

Abstract: In a system for parity encoding data using a low density parity check (LDPC) code, a rate-compatible, irregular LDPC code is generated by extending a base code using a constrained edge growth operation and a parity splitting operation. The base code is a “daughter” code having an encoding rate higher than a designated rate of the LDPC code. The daughter code is progressively extended to lower and lower rates such that each extension code (including the target LDPC code) is compatible with the previously obtained codes. The extension operation may involve introducing a set of new code symbols to the daughter code, by splitting check nodes of a base graph associated with the daughter code, and through constrained edge growth of the base graph. The LDPC code is used to parity encode a data message as a means for forward error correction across a communication channel.

Abstract: An on-chip receiver sensitivity test mechanism for use in an integrated RF transmitter wherein the transmitter and the receiver share the same oscillator. The mechanism obviates the need to use expensive RF signal generator test equipment with built-in modulation capability and instead permits the use of very low cost external RF test equipment. The invention utilizes circuitry already existing in the transceiver, namely the modulation circuitry and local oscillators to perform sensitivity testing. The on-chip LO is used to generate the modulated test signal that otherwise would need to be provided by expensive external RF test equipment with modulation capability. The modulated LO signal is mixed with an externally generated unmodulated CW RF signal to generate a modulated signal at IF which is subsequently processed by the remainder of the receiver chain. The recovered data bits are compared using an on-chip BER meter or counter and a BER reading is generated.

Abstract: In a method of detecting an error pattern in a codeword transmitted across a noisy communication channel, a codeword is detected. A syndrome is then generated by applying a generator polynomial to the codeword. The generator polynomial is adapted to produce a distinct syndrome set for each of “L” (L>1) different error patterns potentially introduced in the codeword during transmission across the communication channel. A type of an error pattern within the codeword is detected based on the syndrome or a shifted version of the syndrome, and then a start position of the error pattern within the codeword.

Abstract: A shift amount measuring apparatus for measuring a phase shift amount of a signal under measurement which is input thereto includes a PLL circuit that generates a strobe signal which is synchronized with a reference signal, a CDR circuit that inputs, into the PLL circuit, a control signal which has a level determined in accordance with a difference in phase between the signal under measurement and the strobe signal, so as to achieve a predetermined difference in phase between the signal under measurement and the strobe signal, and a measuring circuit that, before and after the signal under measurement is phase-shifted, measures a value of the control signal when the predetermined difference in phase is achieved between the signal under measurement and the strobe signal, and calculates the phase shift amount of the signal under measurement based on a difference between the measured levels of the control signal.

Abstract: A method and apparatus for efficiently retransmitting data in a wireless network environment are provided. The method includes transmitting a block comprising one or more data frames to a terminal, receiving an acknowledgement of receipt of the block from the terminal, and retransmitting a block comprising data frames that have not yet been received by the terminal to the terminal by referencing the acknowledgement of receipt. Accordingly, it is possible to enhance overall throughput by reducing receipt acknowledgement time during a data retransmission operation.

Abstract: An H-ARQ system wherein the transmission of two consecutive, or sequential, blocks of information bits are considered jointly; i.e., one of the blocks of information being embedded within the other one of the blocks of information. If a retransmission for the first block is necessary, the system processes both blocks jointly. The system is provided with cross-packet coding which extends current H-ARQ schemes for point-to-point communications wherein the transmission of two consecutive block of information bits is considered jointly. If a retransmission for the first block is necessary, the system processes both blocks jointly. This allows both blocks to be decoded without errors at the receiver after the retransmission.

Abstract: Systems and methods provide an optionally keyed error-correcting code that is spectrally concentrated. Each codeword of the low dimensional spectral concentration code (LDSC code) typically has very few coefficients of large magnitude and can be constructed even with limited processing resources. Decoding can be performed on low power devices. Error-correcting code is constructed around a key using basic computer arithmetic for computations instead of finite field arithmetic, thus saving energy. A recipient who possesses the key enjoys correction of a relatively high percentage of noise errors. In one implementation, a direct list-decoder iteratively estimates a list of message words directly, instead of a list of codewords. In variations, a unique message word is selected from the list either by applying a randomness test or by using message passing.

Abstract: A system and method are used to provide uncorrelated code hopping in a communications system. A shift register receives data. The shift register is clocked to shift the data. A scaler performs a scaling operation on the data with a numerical value of active codes. A truncator truncates the scaled data to its seven most significant bits to produce a pseudo random hop number. A code matrix shifter circularly shifts the active codes in a code matrix based on the pseudo random hop number to produce a circularly shifted code. A transmitter transmits the circularly shifted code.

Abstract: A semiconductor memory has a field programmable unit in which logic to inter-convert external signals to be input/output to/from a memory system and internal signals to be input/output to/from a memory cell array is programmed. A program for constructing the logic of the field programmable unit is stored in a nonvolatile program memory unit. Through the field programmable unit, a controller can access the memory cell array, even when the interface of the controller accessing the semiconductor memory is different from an interface for accessing the memory cell array. Therefore, one kind of semiconductor memory can be used as plural kinds of semiconductor memories. This eliminates the need to develop plural kinds of semiconductor memories, reducing a development cost.

Abstract: A method and system for a non-volatile memory (NVM) with multiple bits error correction are provided and may include detecting bit errors in a memory element, of a NVM array integrated within a chip, which remain uncorrected after forward error correction. A redundant memory element may be utilized when the errors may be detected utilizing a cyclic redundancy check, may be within the NVM array, and may include secure information. Access to the secure information and/or the chip may be disabled when the errors are detected. The FEC operation may include one or both of an error location operation and a correction operation. The errors may be corrected when a location may be known to include the errors. The NVM array may be partitioned into regions. At least one of the redundant memory elements may be substituted in place of the memory element based on a substitution priority.

Abstract: A decoding device for decoding LDPC (Low Density Parity Check) codes includes a message calculation unit for performing a variable node calculation for decoding the LPDC codes using a message to be supplied, or performing a check node calculation, and outputting the message to be obtained as a result of the calculation, a storing unit for storing the message, and a control unit for performing writing control for writing the message that the message calculation unit outputs in the storing unit, and readout control for reading out the same message to be employed for the calculation of the message calculation unit from the storing unit twice, and supplying these to the message calculation unit.

Abstract: A system, method and data structure for error correction for use in the transmission of content data distribution networks uses a compressed memory, for example a bitmap, to identify portions of transmitted content data files where transmission errors have occurred. The error memory, is used to generate an error status report that is returned to a transmission controller via a low bandwidth back channel, for example the Internet. The information in multiple error status reports is aggregated by the control system of the transmitter and used to re-transmit those portions of previously transmitted content data files that were not properly received due to error. By re-transmitting only the data packets of the transmitted content data files that contain errors, overall transmission speed is increased and bandwidth usage is conserved.

Abstract: Data is read from a memory array. Before being stored in a data buffer, a Hamming code detection operation and a Reed-Solomon code detection operation are operated in parallel to determine if the data word has any errors. The results of the parallel detection operations are communicated to a controller circuit. If an error is present that can be corrected by the Hamming code correction operation, this is performed and the Reed-Solomon code detection operation is performed on the corrected word. If the error is uncorrectable by the Hamming code, the Reed-Solomon code correction operation is performed on the word.

Abstract: A transmitter generates error correction data according to an error correction scheme that logically arranges the communication data in a number of rows and a number of columns. The transmitter transmits the communication data and the error correction data. A receiver receives the communication data and the error correction data. The receiver processes the error correction data to correct errors in the communication data. The receiver generates information regarding the errors in the communication data. The transmitter processes the information to alter at the number of rows and/or the number of columns.

Abstract: Techniques to cause a point-to-point link between system components to engage in a negotiation process that may lead to the link transitioning from an active state in which data may be transmitted between system components to a low power state where data may not be transmitted. The negotiation process may occur between each pair of nodes within an electronic system that are interconnected via point-to-point link. The negotiation may ensure that there are no pending transactions or transactions that may occur within an upcoming period of time. Through this negotiation each component acknowledges and agrees to transition the link to the low power state.

Abstract: A method and apparatus for selecting interleaver sizes for turbo codes is provided herein. During operation information block of size K is received. An interleaver size K? is determined that is related to K?, where K? from a set of sizes; wherein the set of sizes comprise K?=ap×f, pmin?p?pmax; fmin?f?fmax, wherein a is an integer and f is a continuous integer between fmin and fmax, p takes integer values between pmin and pmax, a>1, pmax>pmin, pmin>1. The information block of size K is padded into an input block of size K? using filler bits, if needed. Encoding is performed using the original input block and the interleaved input block to obtain a codeword block using a turbo encoder. The codeword block is transmitted through the channel.

Abstract: A method and apparatus for Turbo encoding uses a set of rate-compatible Turbo Codes optimized at high code rates and derived from a universal constituent code. The Turbo Codes have rate-compatible puncturing patterns. The method comprises: encoding a signal at a first and second encoder using a best rate 1/2 constituent code universal with higher code rates, the first encoder and the second encoder each producing a respective plurality of parity bits for each information bit; puncturing the respective plurality of parity bits at each encoder with a higher rate best puncturing patterns; and puncturing the respective plurality of parity bits at each encoder with a lower rate best puncturing pattern. In a variation, the best rate 1/2 constituent code represents a concatenation of polynomials 1+D2+D3 (octal 13) and 1+D+D3 (octal 15), D a data bit. A Turbo Encoder is provided which has hardware to implement the method.