Abstract: Shift resister rings are used to provide column access in a traceback memory during Viterbi decoding.

Abstract: A method and system for decoding a received data stream are disclosed. The appropriate time interval to decode the received data stream is derived from the data stream itself. A header of the data stream is analyzed to determine two sets of time ranges, each set of time ranges corresponding to a set of possible data transmission intervals. A preamble of the header contains timing information for development of a first set of time ranges to decode a synchronization word of the header. The synchronization word contains both data information and timing information to develop the second set of time ranges. The data information included in the header is used validate the data stream for the receiving device. The second set of time ranges is used to decode a data payload portion of the data stream.

Abstract: A method and apparatus is provided for receiving data in a receiver of a communication system. In the receiver, a first calculator calculates a Log Likelihood Ratio (LLR) value of data transmitted from a transmitter, a decoder performs iterative decoding on the transmitted data using the LLR value calculated by the first calculator. A second calculator determines whether there is an error in the decoded data by calculating an error of the data decoded by the decoder. A storage stores an LLR value of the decoded data according to the determination result of the second calculator. An adder adds up the LLR value calculated by the first calculator and the LLR value stored in the storage.

Abstract: Iterative decoding channel architectures employing coded modulation are provided. The coded modulation is realized via set partitioning for Partial Response (PR) channels along with multi-level coding. Associated error correction encoding and decoding methods, with additional compatibility considerations for channel constrained coding, are also provided.

Abstract: A method of terminating two or more constituent encoders of a turbo encoder employing a turbo code, comprising the step of: generating tail input bits at each of two or more constituent encoders, including deriving the tail input bits from each of the two or more constituent encoders separately from a contents of shift registers within each of the two or more constituent encoders, after an encoding of information bits by the two or more constituent encoders; puncturing one or more tail output bits such that 1/R output tail bits are transmitted for each of a plurality of trellis branches, wherein R is a turbo code rate employed by the turbo encoder during an information bit transmission. In yet another variation, the step of puncturing the tail output bits further comprises the step of: transmitting, during trellis termination, the tail output bits, only if they are sent from an output branch of one of the two or more constituent encoders that are used during information bit transmission.

Abstract: An apparatus and method are provided for stopping iterative decoding in a channel decoder of a mobile communication system. Constituent decoding of received signals is performed and decoded signals are output. Hard decision processes for the decoded signals are performed and hard-decided signals are output. The hard-decided signals are cyclic redundancy check (CRC) encoded, and a determination is made as to whether the parities are identical and iterative decoding is stopped according to a determination result.

Abstract: A semiconductor device has multilevel memory cells, each cell storing at least three levels of data each. At least a first data composed of first data bits and a second data composed of second data bits are arranged in order that at least a bit of an N-order of the first bits and a bit of the N-order of the second bits are stored in one of the cells, the N being an integral number. A voltage corresponding to the N-order bits is generated and applied to the one of the cells in response to an address information corresponding thereto. Another semiconductor device has multilevel memory cells arranged so as to correspond to a physical address space, each cell storing 2n levels of data each expressed by n (n?2) number of bits (X1, X2, . . . , Xn). A logical address is converted into a physical address of the physical address space. Judging is made whether a logical address space including the logical address matches the physical address space.

Abstract: Embodiments include a DRAM cache structure, associated circuits and method of operations suitable for use with high-speed caches. The DRAM caches do not require regular refresh of its data and hence the refresh blank-out period and refresh power are eliminated, thus improving cache availability and reducing power compared to conventional DRAM caches. Compared to existing SRAM caches, the new cache structures can potentially achieve the same (or better) speed, lower power and better tolerance to chip process variations in future process technologies.

Abstract: A decoder architecture and method for processing codewords are provided. In one implementation, the decoder architecture includes an input buffer configured to receive and store one or more codewords to be processed, and a decoder configured to receive codewords one at a time from the input buffer. The decoder processes each codeword only for a minimum amount of time for the codeword to become error free. The decoder architecture further includes an input buffer monitor and supply regulator configured to change a voltage supply to the decoder responsive to an average amount of time or each codeword to become error free.

Abstract: An order-ensemble searching unit classifies a distribution of reception signals at each bit position of a modulation symbol, and searches an order ensemble of a parity check matrix that minimizes an SNR threshold value. A code generating unit generates a parity check matrix and a generation matrix, based on the order ensemble obtained as a search result.

Abstract: An iterative error correcting decoder is provided. In one implementation, the iterative error correcting decoder includes an equality constraint node and a parity check node, the parity check node. The parity check node includes parity logic configured to receive input data bits from the equality constraint node and determine a first minimum value and a second minimum value associated with the input data bits using a MinSum algorithm. An enhancement function is performed on the first minimum value and the second minimum value. The enhancement function compares each of the first minimum value and the second minimum value with a first pre-determined constant value, and responsive to the first minimum value and the second minimum value being smaller than the first pre-determined constant value, the enhancement function passes the first minimum value and the second minimum value without any changes as output of the MinSum algorithm.

Abstract: A method (700) and apparatus (600) are described for performing parallel decoding in connection with 2M-1 parallel ACS unit in ACS unit (110), track buffer (112) and voting unit (114) in an Ultrawide Bandwidth (UWB) receiver having a parallel trellis decoder for decoding a message sequence encoded according to a convolutional code. Outputs from the track buffer can be input to a voting unit (114) where a voting scheme can be applied and a decision rendered as to the originally transmitted message sequence.

Abstract: Methods and systems for configuring characteristics associated with at least one portion of a memory array comprising addressable units are provided. In one aspect, a method for controlling a power supply voltage for a memory array comprises detecting whether an error occurred in performing a read operation on an addressable unit of the memory array using a first power supply voltage coupled to the memory array. The method further comprises incrementing an error counter for tracking an error count associated with the memory array and switching the memory array to a second power supply voltage if the error count is equal to or exceeds an error threshold for the memory array. The method further comprises, based on at least one condition, switching the memory array to the first power supply voltage and resetting the error counter to an initial value.

Abstract: A method and apparatus are provided for implementing enhanced vertical ECC storage in a dynamic random access memory. A dynamic random access memory (DRAM) is split into a plurality of groups. Each group resides inside a DRAM row address strobe (RAS) page so that multiple locations inside a group can be accessed without incurring an additional RAS access penalty. Each group is logically split into a plurality of segments for storing data with at least one segment for storing ECC for the data segments. For a write operation, data are written in a data segment and then ECC for the data are written in an ECC segment. For a read operation, ECC are read from an ECC segment, then data are read from the data segment.

Abstract: A method of terminating two or more constituent encoders of a turbo encoder employing a turbo code, comprising the step of: generating tail input bits at each of two or more constituent encoders, including deriving the tail input bits from each of the two or more constituent encoders separately from a contents of shift registers within each of the two or more constituent encoders, after an encoding of information bits by the two or more constituent encoders; puncturing one or more tail output bits such that 1/R output tail bits are transmitted for each of a plurality of trellis branches, wherein R is a turbo code rate employed by the turbo encoder during an information bit transmission. In yet another variation, the step of puncturing the tail output bits further comprises the step of: transmitting, during trellis termination, the tail output bits, only if they are sent from an output branch of one of the two or more constituent encoders that are used during information bit transmission.

Abstract: Provided are a Vestigial Side Band (VSB) Digital Television (DTV) transmitter and receiver based on the Advanced Television System Committee (ATSC) A/53, and a method thereof. The present invention provides 8-VSB DTV transmitter and receiver that can improve reception performance of the receiver by transmitting and receiving robust data mixed with P-2VSB, E-4VSB, and/or E-8VSB. The DTV transmitter includes an input means for receiving a digital video data stream including normal data and robust data; an encoding means for coding the digital video data stream into data symbols; and a transmitting means for modulating and transmitting an output signal of the encoding means, wherein the encoding means performs trellis coding on the robust data by sequentially applying a plurality of trellis coding methods.

Abstract: Embodiments of the invention are generally directed to improving the reliability, availability, and serviceability of a memory device. In some embodiments, a memory device includes a memory core having a first portion to store data bits and a second portion to store error correction code (ECC) bits corresponding to the data bits. The memory device may also include error correction logic on the same die as the memory core. In some embodiments, the error correction logic enables the memory device to compute ECC bits and to compare the stored ECC bits with the computed ECC bits.

Abstract: A system may comprise a condition detection system that includes change circuitry configured to detect a change for at least one predetermined bit of an N-bit bus, where N is a positive integer, and to provide a corresponding change signal indicative of the detected condition. Match circuitry is configured to detect a match condition for up to a selected subset of predetermined bits of the N-bit bus and to provide a corresponding match signal indicative of the detected condition. Selection circuitry is programmable to provide a selected one of the change signal and the match signal as a corresponding output signal.

Abstract: The systems and methods described herein provide a redundant communication path. The systems and methods can provide a second source for the same data under many circumstances. These circumstances can include, for example, 1) when data incurs errors during transmission in the communication link network, 2) when a communication link in the communication link network experiences transient blockage, 3) when a communication link experiences prolonged or indefinite blockage, and 4) when an optical transceiver unit within the communication link network experiences a hardware failure and is unable to perform its tasks.

Abstract: A channel coding device is disclosed. In the device, a bit inserter inserts known bits in an input data bit stream at predetermined positions. A channel coder codes the bit-inserted data bit stream to generate coded symbols. A rate matcher matches a rate of the coded symbols to a given channel symbol rate. A channel interleaver interleaves the rate matched channel symbols. The rate matcher includes a puncturer for puncturing the inserted known bits included in the coded symbols when the coded symbol rate is higher than the given channel symbol rate. The rate matcher includes a repeater for repeating the coded symbols to match the coded symbol rate to the given channel symbol rate when the coded symbol rate is lower than the given channel symbol rate.