Abstract: An LDPC decoder, applicable to LDPC codes including codes where check nodes within the same group are connected to a common bit node, successively processes groups of check nodes in a particular iteration, including updating bit nodes in that same iteration responsive to messages generated in response to processing a group of check nodes. Within an iteration, the LDPC decoder may also track the number of unresolved parity check equations, and cease iterating or output to an outer block decoder if that number reaches a local minima or standard minimum, falls below a predetermined threshold, or its rate of change falls below a predetermined threshold, indicating a lack of convergence or false convergence condition. The LDPC decoder may also provide a feedback assist to a demodulator. Also, a novel memory configuration may store messages generated by the decoder in the course of check node processing.

Abstract: Methods and devices for encoding in parallel a set of data bits for use in communications systems. The set of data bits to be encoded is divided into two subsets with the first subset being encoded in parallel using the second subset. The first subset is also encoded in parallel using the second subset. The first subset is also encoded in parallel using a subset of an immediately preceding set of data bits. Parallel encoding is realized by using an encoding module utilizing multiple single bit submodule. Each submodule receives a single bit from the first subset and either the second subset or the subset of the immediately preceding data set. Each single bit submodule produces a pair of output bits from the convolutional encoding of a single bit of the first subset and either the second subset or the subset of the immediately preceding data set. The multiple single bit submodules operate in parallel to simultaneously and collectively produce a set of data bits.

Abstract: The disclosed technology provides systems and methods for identifying potential error locations, patterns, and likelihood metrics in connection with trellis-based detection/decoding. In one aspect of the invention, the disclosed technology detects information that was previously encoded based on a trellis, and decodes the detected information based on the trellis to provide decoded information. The decoded information corresponds to a winning path through the trellis that ends at a winning state. The disclosed technology can identify one or more alternate paths through the trellis that also end at the winning state, and can generate a potential error pattern for each of the alternate paths.

Abstract: A parity adder obtains a second data by adding a parity for first data to be written to a memory to the first data. An access-key register holds an access key unique to a source of request. A first operating unit obtains a third data by calculating an XOR between the second data and the access key, the access key being set by the source of request for writing data to the memory. A second operating unit obtains a fourth data by calculating an XOR between the access key and the third data. A syndrome calculator calculates a syndrome from the third data, the access key being set by the source of request for reading data from the memory. A determining unit determines whether to output the third data as the first data, based on calculated syndrome.

Abstract: A facsimile machine receives image data from a facsimile machine of another end. A Random Access Memory (RAM) stores a measured average value and fluctuation of an Eye Quality Monitor (EQM) value of the image data, and a number of error lines of the image data as an EQM data table. In past facsimile communication, a main control unit receives a training signal from the facsimile machine of the other end, and executes a training process. The main control unit measures an average value and fluctuation of an EQM value of the training signal, and compares the measured average value and the fluctuation of the EQM value with the average value and the fluctuation of the EQM value stored in the EQM data table. When there is no match, the main control unit executes the training process again.

Abstract: An access control apparatus includes a parity generator that generates a parity for original data to be written into a memory; and a parity adder that generates parity-added data by adding the parity to the original data; a first syndrome generator that generates a first syndrome of first mask data to mask the parity-added data. The first syndrome is a value associated beforehand with a first access code to be used when a writer accesses the memory. The apparatus also includes a first mask generator that generates the first mask data based on the first syndrome, the first access code, and a first memory address; a first XOR unit that obtains first post-operation data by calculating an XOR between the parity-added data and the first mask data; and a writing unit that writes the first post-operation data into the memory.

Abstract: The search key and key fields of a CAM in a cache are encoded with a Hamming distance of at least two to increase the speed of the CAM by ensuring each mismatching match line is discharged by at least two transistors in parallel. Where the cache is physically tagged, the search key is a physical address. The page address portion of the physical address is encoded prior to being stored in a TLB. The page offset bits are encoded in parallel with the TLB access, and concatenated with the encoded TLB entry. If a page address addresses a large memory page size, a plurality of corresponding sub-page addresses may be generated, each addressing a smaller page size. These sub-page addresses may be encoded and stored in a micro TLB. The encoded key and key field are tolerant of single-bit soft errors.

Abstract: A method of interleaving blocks of indexed data of varying length is disclosed. The method includes the steps of: providing a set of basic Interleavers comprising a family of one or more permutations of the indexed data and having a variable length; selecting one of the basic Interleavers based upon a desired Interleaver length L; and adapting the selected basic Interleaver to produce an Interleaver having the desired Interleaver length L.

Abstract: A turbo decoder iteratively decodes a received, encoded signal with one or more constituent decoders employing a simplified log-maximum a posteriori (SMAP) decoding algorithm. The SMAP decoding algorithm calculates reliability information as a log likelihood ratio for a log-MAP algorithm using a reduced set of path metrics recursively updated based on maximum likelihood recursion. Updated extrinsic information for a subsequent decoding may be derived from the LLR calculated by the SMAP decoding algorithm.

Abstract: A dual ported replicated data cache. The cache is configured for storing input data blocks. The cache includes an augmenter for producing an augmented data block with parity information from the input data block, a first memory array for storing the augmented data block, and a second memory array for storing the augmented data block.

Abstract: A first device receives first data that includes a plurality of input vectors, which includes a primary input vector and a set of secondary input vectors and detects uncorrectable errors in the first data based on a quality metric indication. Based on detecting the uncorrectable errors in the first data, the first device substitutes a predetermined codeword for the primary input vector encoded using a non-perfect code, and substitutes a predetermined input vector for the primary input vector. The first device modulates a set of encoded secondary input vectors using the predetermined input vector to generate a modulated set of encoded secondary input vectors and transmits as second data the predetermined codeword and the modulated set of encoded secondary input vectors to a target device, wherein the substituting step creates a first number of errors that is detected by the target device as uncorrectable errors in the transmitted second data.

Abstract: A method for puncturing a Low Density Parity Check (LDPC).

Abstract: A radio frequency identification (RFID) decoding subsystem includes a pre-decode module and a decode module. The pre-decode module is coupled to process down-converted RFID signals into at least one of pre-decoded baseband data and corresponding decoding information. The decode module is coupled to process the pre-decoded baseband data into decoded RFID data, where the processing of the pre-decoded baseband data is based on the corresponding decoding information when the corresponding decoding information is produced by the pre-decoder module.

Abstract: A packet including data and a cyclic redundancy check code is encoded by using a selectable one of N scrambling codes (N>1). The encoded packet is transmitted and received, then decoded N times by using the N scrambling codes. The cyclic redundancy check code is used to decide which one of the N scrambling codes enabled the encoded packet to be decoded correctly, and the correctly decoded data are used. Packets with different formats, in particular with headers of different lengths, can be distinguished by the use of different scrambling codes, so that different formats can be employed without the need to transmit extra data to indicate which format has been used.

Abstract: The described methodology provides users with the ability to specify flexible encryption options in a storage system using RAID technology. The users can use the system to achieve a configuration which achieves a desired balance between security and system load/performance. Specifically, one aspect of the methodology enables the user to enable or disable the encryption of the redundant parity information. Change of the data causes change of the parity information and, when parity is not encrypted, a close analysis of parity change may enable one to reconstruct the all or some of the encrypted data. Therefore, when a user chooses the encryption of the parity information, it becomes more difficult to reconstruct the plain data from the encrypted data. The described storage system also provides a function for monitoring and reporting the current or projected utilization of various computer resources including processor and memory utilization, which assists the user in selecting the proper security option.

Abstract: Systems, methods and computer program products for providing a nested two-bit symbol bus error correcting code. Methods include constructing a nested error correcting code (ECC) scheme. The method includes receiving a Hamming distance n code. A symbol correcting code H-matrix is created by iteratively adding rows of H-matrix bits on a symbol column basis such that the symbol correcting code H-matrix describes a symbol correcting code, and the Hamming distance n code is preserved as a subset of the symbol correcting code H-matrix.

Abstract: Feedback and frame synchronization between media encoders and decoders is described. More particularly, the encoder can encode frames that are based on source content to be sent to the decoder. The encoder can determine whether the frame should be cached by the encoder and the decoder. If the frame is to be cached, the encoder can so indicate by encoding the frame with one or more cache control bits. The decoder can receive the frame from the decoder, and can examine the cache control bits to determine whether to cache the frame. The decoder can also decode the frame.

Abstract: Techniques to cause a point-to-point link between system components to engage in a negotiation process that may lead to the link transitioning from an active state in which data may be transmitted between system components to a low power state where data may not be transmitted. The negotiation process may occur between each pair of nodes within an electronic system that are interconnected via point-to-point link. The negotiation may ensure that there are no pending transactions or transactions that may occur within an upcoming period of time. Through this negotiation each component acknowledges and agrees to transition the link to the low power state.

Abstract: A turbo-like code is formed by repeating the signal, coding it, and interleaving it. A serial concatenated coder is formed of an inner coder and an outer coder separated by an interleaver. The outer coder is a coder which has rate greater than one e.g. a repetition coder. The interleaver rearranges the bits. An outer coder is a rate one coder.

Abstract: A memory using techniques to extract the data content of its storage elements, when the distribution of stored states is degraded, is presented. If the distribution of stored states has degraded, secondary evaluations of the memory cells are performed using modified read conditions. Based upon the results of these supplemental evaluations, the memory device determines the read conditions at which to best decide the data stored.