Abstract: A method for testing functionality on a JAVA enabled device is provided. The method includes downloading a test to the JAVA enabled device from a management unit having access to the test. The management unit is connected with a partner device polling the management unit. A message is forwarded from the JAVA enabled device to the partner device through the management unit. The expected content of the message is forwarded from the JAVA enabled device to the partner device, through the management unit. The message is then compared to the expected content. A system and a graphical user interface are also included.

Abstract: The present invention relates to a method for scheduling data retransmissions, a method for use in a data retransmission scheme and a method for updating a soft buffer of a base station in a mobile communication system during a soft-handover. The present invention relates to a base station executing the controlling and updating method, a communication terminal for executing the scheduling method and to a mobile communication system comprising at least one the base station and communication terminal. To prevent erroneous combining of data packets in a packet retransmission scheme at the receiver, the present invention provides a method that may flush the soft buffer region associated to a received data packet upon its correct reception. Further, a method is provided that monitors the time elapsed since the last storing of a data packet in a buffer region of a base station to be able to trigger the flush of the buffer region upon expiry of a threshold time period.

Abstract: Reconfigurable communications infrastructures may be implemented to interconnect ASIC devices (e.g., FPGAs) and other computing and input/output devices using high bandwidth interconnection mediums. The computing and input/output devices may be positioned in locations that are physically segregated from each other, and/or may be provided to project a reconfigurable network across a wide area. The reconfigurable communications infrastructures may be implemented to allow such computing and input/output devices to be used in different arrangements and applications, e.g., for use in any application where a large array of ASIC devices may be usefully employed such as supercomputing, etc.

Abstract: In a nonvolatile memory system, data is read from a memory array and used to obtain likelihood values, which are then provided to a soft-input soft-output decoder. The soft-input soft-output decoder calculates output likelihood values from input likelihood values and from parity data that was previously added according to an encoding scheme.

Abstract: In a communication system, a signal transmission apparatus includes an encoder for encoding an information vector into a low density parity check (LDPC) codeword with an LDPC coding scheme, and a puncturer for puncturing the LDPC codeword according to a coding rate using a puncturing scheme. A signal reception apparatus includes a ‘0’ inserter for inserting ‘0’ symbols in a received signal according to a coding rate used in a signal transmission apparatus, and a decoder for decoding the ‘0’ symbol-inserted signal with a decoding scheme corresponding to a low density parity check (LDPC) coding scheme used in the signal transmission apparatus, thereby detecting an information vector.

Abstract: Simplified RS (Reed-Solomon) code decoder that obviates error value polynomial calculation. A novel means is presented herein by which error magnitudes (or error values) can be calculated directly without requiring the generation of an error value polynomial (EVP). Modification of the Koetter decoding approach and the Forney formula are employed herein to perform the direct calculation of the error values. This approach is operable to save computation clock cycles that would normally be used to compute the EVP, and these clock cycles may be used to reduce the otherwise required parallelism and complexity in the ECC design that may be needed to perform the error correction in the allotted time and may also result in power savings. Some advantages related to this may approach include lower risk, less design time, and more scalability in an overall design.

Abstract: An Add-Compare-Select circuit for use with a trellis decoder can include a first module and a second module. The first module can provide a difference signal specifying an indication of a difference between a second path cost and a first path cost of a trellis. The second path cost can be a sum of a second state cost and a second branch metric and the first path cost can be a sum of a first state cost and a first branch metric. The second module can select the first path cost or the second path cost as a new cost according to the difference signal of the first module.

Abstract: Systems, methods, and computer-readable memory media for performing various computer configuration tasks are disclosed. One such configuration task is dissimilar system restore (DSR). Another such task is software deployment. In various embodiments, these configuration tasks operate on a target computer system using a utility operating system to perform detection of certain target system devices, determination of critical device classes on the source computer system, and updating of target computer configuration settings. Other tasks may be performed upon a computer system such as a backup server. These tasks include locating device drivers for the target operating systems and the installing utility operating system, as well as creating device driver packages that are usable to install device drivers for a plurality of devices.

Abstract: A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device may include a first memory cell array block generating first data, a second memory cell array block generating second data, and first and second error detection code generators. The first error detection code generator may generate a first error detection code and may combine a portion of bits of the first error detection code with a portion of bits of a second error detection code to generate a first final error detection signal. The second error detection code generator may generate the second error detection code and may combine the remaining bits other than the portion of bits of the second error detection code with the remaining bits other than the portion of bits of the first error detection code to generate a second final error detection signal.

Abstract: In order to correct an error in input data to thereby obtain write data, in a memory core, an EXOR element performs arithmetic processing based on an output result of an output data latch for latching read data and a result of inputted array input data, and a selector selects a result of the arithmetic processing to prepare write data. Thus, data obtained after performance of the arithmetic processing can be generated in a semiconductor memory by an operation performed immediately after data read. In addition, it is unnecessary to transfer data to an external logic circuit. Therefore, the result of the arithmetic processing can be written to a memory cell block in a subsequent clock.

Abstract: Data move operations in a memory device are described that enable identification of data errors. Error detection circuitry in the memory device can be operated using parity data or ECC data stored in the memory. Results of the error detection can be accessed by a memory controller for data repair operations by the controller.

Abstract: A communication apparatus that is present between each of receiver and sender LANs including a user network and a WAN, and relays a packet exchanged between the sender and receiver LANs through the WAN while correcting an error in the packet. The communication apparatus determines whether to perform error correction on a packet received from the sender LAN. When it is determined not to perform the error correction, the communication apparatus instantly transfers the packet to the receiver LAN.

Abstract: A method and system for error detection in programs with collective synchronization and/or procedures are provided. In one aspect, the method and system may use interprocedural analysis for matching synchronizations in a program in order to detect synchronization errors, and, if no such errors exist, may determine the synchronization phases of the program. The method and system in one aspect may use a combination of path expressions and interprocedural program slicing to match the synchronization statements that may execute along each program path. If the synchronization matching succeeds, the method and system in one aspect may determine the sets of synchronization statements that synchronize together. A matching failure may indicate the presence of a synchronization error and the method and system in one aspect may construct a counter example to illustrate the error.

Abstract: An apparatus for generating a detected punctured position in punctured convolutional codes. A delay line circuit has a plurality of delay elements connected in series, storing a finite sequence of an input bit stream. A logic gate circuit, coupled to outputs of a part of the delay elements of the delay line circuit in accordance with a parity check polynomial, performs a logic operation to output a number stream. The number stream is accumulated for possible punctured positions and the one of the possible punctured positions with a minimal accumulated number is selected and determined as the detected punctured position.

Abstract: In a Viterbi decoding apparatus, deterioration in error correcting capability before and after a terminated code is controlled. A termination timing detection unit (103) detects a termination timing of a Viterbi code, a compulsion generation unit (105) generates a compulsion value so as to pass a specific path at the termination timing and timings before and after the termination timing, and the compulsion value is set on a traceback pointer (106). Therefore, even when the decoding state of a code before termination is degraded, decoding of a next code can be carried out without being affected by the degradation, thereby improving error correcting capability.

Abstract: A network for channel coding permutation and de-permutation comprises: a first side and a second side, each of which has at least one terminal. The network further comprises: two or more columns of nodes located between the first and second sides. A first column of the columns interfaces the first side, and a second column of the columns interfaces the second side. Each of the columns comprises at least one node. Each node of the columns is connected to a first number of nodes of each of adjacent columns next to the columns. The first number is identical for all the nodes in the network. The nodes which are selected as switches are concurrently controlled to perform switching operations.

Abstract: An apparatus, a carrier medium storing instructions to implement a method, and a method in a node of a wireless network able to receive packets that exactly or substantially conform to a wireless network standard according to which each packet includes a header having bits that have respective correct values in the case that the packet exactly conforms to the standard. The method includes receiving a start-of-packet (SOP) trigger that indicates that a packet may have been received, checking one or more bits in the header to determine whether or not they have their respective correct values, and continuing to process the packet in the case that the checking indicates that the checked bits have their respective correct values. In one implementation, the header includes a first field modulated at a known rate that has one or more reserved bit locations, and a second field modulated at a data rate indicated in the first field.

Abstract: The present invention relates to a method of operating an electronic device and an electronic device. The electronic device comprises a signal path for transmitting data, an input/output interface connected with the signal path, a masking circuit and an error calculation circuit. The masking circuit is connected with the signal path and the error calculation circuit. The error calculation circuit is connected with the signal path. The signal path is connected with the masking circuit to deliver masking information to the masking circuit. The masking circuit considers the received masking information for masking the data and delivers the masked and non-masked data to the error detection circuit.

Abstract: A digital broadcast transmitting/receiving system and a method for processing data are disclosed. The method for processing data may enhance the receiving performance of the receiving system by performing additional coding and multiplexing processes on the traffic information data and transmitting the processed data. Thus, robustness is provided to the traffic information data, thereby enabling the data to respond strongly against the channel environment which is always under constant and vast change.

Abstract: Cyclic-redundancy-code (“CRC”) information that is received along with a frame from a fiber-channel is stored in an on-chip frame buffer, and later checked to ensure the integrity of the data while in the frame buffer. In various embodiments, data frames, along with their CRC information, are stored into a data-frame buffer, and/or non-data frames along with their CRC information are stored into a receive-non-data-frame buffer. The improved communications channel system includes a channel node having dual ports, each port supporting a fiber-channel arbitrated-loop serial communications channel. The serial communications channels each include CRC on data transmissions on the channel, an on-chip frame memory located on-chip in the channel node that receives a data frame and the frame's associated CRC from the communications channel, and an integrity apparatus that later uses the received associated CRC for data-integrity checking of data in the on-chip frame memory.