Abstract: A method of decoding a received signal encoded with an LDPC code is provided. The method comprises initializing bits with an initial value of the received signal, obtaining posterior values of the bits by iteratively decoding the bits in a row direction and a column direction, determining on the basis of the posterior values whether an iterative decoding operation should be performed and comparing the posterior values with predetermined values and updating the initial value of the bits, when it is determined that the iterative decoding operation is be performed.

Abstract: Systems and methods are provided to correct errors occurring in a decision-codeword that is generated by a detector. A decoder determines whether errors in the decision-codeword are of a degree that exceeds the correction capability of a Reed-Solomon error-correction code. If they are, the decoder iteratively modifies the decision-codeword to reduce the number of errors therein. In each iteration, the decoder generates an error indicator using one or more error indicators from a previous iteration and uses the error indicator to perform error detection and correction operations.

Abstract: A method and system for improving buffer compression in automatic retransmission request (ARQ) systems includes both a compander and decompander for further processing data. A received data string k bits in length is first companded according to a predetermined companding scheme. The companded data string is reduced to a length of k?1 bits for more efficient storage. Upon receipt of a request for retransmission, the stored companded data string is loaded and decompanded back to a length of k bits. Once decompanded, the data string is combined with a retransmitted data string to produce a single data string with an increased likelihood of being correct. By companding the data string before storage, a smaller memory block can be used for the storage of the data string.

Abstract: A device-specific value is reliably generated in a device. In a first component of the device, a first digital value is generated that is substantially dependent fabrication variation among like device. Redundancy information is computed based on the first digital value. A subsequent digital value is later generated in the first component of the device. The first digital value is then determined in a second component of the device from the subsequent digital value and the redundancy information.

Abstract: A semiconductor memory module comprises a control chip for driving ECC memory chips and further memory chips. The memory chips are arranged in two rows on a top side and a bottom side of the module circuit board. The ECC memory chips are arranged centrally on the module circuit board alongside the rows of the memory chips. A control bus connects the ECC memory chips and also the memory chips to the control chip. In a region remote from the control chip, the control bus branches in a contact-making hole into a first partial bus, to which a first group of memory chips are connected, and a second partial bus, to which a second group of memory chips are connected. The ECC memory chips are likewise connected to the control bus via the contact-making hole. Since the ECC memory chips are not arranged directly under the control chip, a bus branch directed backward is not required. As a result, space considerations on the module circuit board are eased and signal integrity on the control buses is improved.

Abstract: A method of stabilizing an identification series of bits by iteratively reading the identification series and logical OR'ing the identification series with a mask string after each read of the identification series. This produces a mask string having a first value in all positions of the mask string where bits in the identification series have never changed value during all of the readings of the identification series, representing stable bits, and a second value in all positions of the mask string where bits in the identification series have changed value during at least one of the readings of the identification series, representing unstable bits. The number of the unstable bits in the mask string having the second value is counted, and a method failure code is selectively reported when the number of unstable bits exceeds a maximum allowable number of unstable bits. An identification string is produced from the stable bits, and an identification code is calculated from the identification string.

Abstract: An apparatus and method of reducing power dissipation in a register exchange implementation of a Viterbi decoder used in a digital receiver or mass-storage system without degrading the bit error rate of the decoder, by selectively inhibiting data samples in the Viterbi decoder's register memory from being shifted if the data samples have converged to a single value. FIFO memories keep track of what data samples have converged, the order of the samples, and the converged data value, thereby keeping the decoded data in the FIFO synchronized with data continuing to be shifted through the register memory.

Abstract: A system and method are used to provide uncorrelated code hopping in a communications system. A multi-bit linear shift register receives data and clocks the data fifteen times. A word assembler receives the shifted data and outputs a fifteen bit word. A mixer mixes the fifteen bit word with an numerical value of active codes to generate a mixed signal. A divider divides the mixed signal to produce a divided signal. A truncator truncates the divided signal to its seven most significant bits to produce a pseudo random hop number. A code matrix shifter circularly shifts the active codes in a code matrix based on the pseudo random hop number to produce a circularly shifted code. A transmitter transmits the circularly shifted code matrix.

Abstract: Significant improvement in Raptor codes and punctured LDPC codes are obtainable by use of the invention. In both a transmission scheme for Raptor-encoded or LDPC-encoded information, a dynamic adjustment approach is employed. A fraction of a codeword or information frame is transmitted. A feedback signal is sent from the receiver to the transmitter indicating either 1) successful decoding, or 2) failure to decode and/or a feedback signal indicative of a statistical measure of transmission channel quality. If decoding fails, a further portion of the codeword or frame is sent. The intensity and/or size of the fraction is adjusted based on the feedback signal. In one embodiment, a specific range for probabilities employed in the encoding process for Raptor codes provides the ability to increase transmission throughput. Further it has been found that the advantageous Raptor codes are useful in noise conditions where even the improved punctured LDPC codes of the invention begin to degrade.

Abstract: In a forward error correction method and a forward error correction addition apparatus, error correction is performed on the basis of data, to which forward error correction code is added, transmitted through a network to output decoded data. The data transmitted through the network includes information bits represented by an information bit matrix with n rows and m columns (n, m are natural numbers), and redundancy bits represented by an odd number of redundancy information bit rows and an odd number of redundancy information bit columns based on the information bit matrix, which are provided in the row direction and in the column direction of the information bit matrix respectively. The redundancy bits are the forward error correction code.

Abstract: Clocking Chien searching at different frequency than other Reed-Solomon (RS) ECC decoding functions. An efficient implementation allows for a fast clock signal to govern the operation of the more computationally and time-intensive portions of the error correction code (ECC) time budget. For example, at least one module and/or decoding function within the ECC decoding is governed by using a first clock signal, and at least one other module and/or decoding function (or all the other modules and/or decoding functions) is/are governed by using a second clock signal. In one implementation of Reed-Solomon (RS) decoding, the Chien searching function is operated using a faster clock signal than at least one other RS error correction decoding function thereby allowing for a significant reduction in area and power than other architectural trade-offs.

Abstract: Improved LDPC code structure and concatenation rules for IEEE 802.11n systems, providing two code sets per rate, one longer codeword and one shorter codeword. The longer codeword length is determined by the system parameters, while the shorter codeword length is ? of the longer codeword length. A LDPC concatenation rule is provided, wherein a maximum of one extra OFDM symbol is added in padding in order to reduce the code set granularity. In order to provide improved code performance, more bits are shortened compared with puncturing, by transmitting the extra OFDM symbol. Further, all the required puncturing and shortening bits are distributed across all codewords. This scheme provides a preferred tradeoff between code complexity and over-the-air efficiency.

Abstract: A method of interleaving blocks of indexed data of varying length is disclosed. The method includes the steps of: providing a set of basic Interleavers comprising a family of one or more permutations of the indexed data and having a variable length; selecting one of the basic Interleavers based upon a desired Interleaver length L; and adapting the selected basic Interleaver to produce an Interleaver having the desired Interleaver length L.

Abstract: Encoders and methods for designing encoders for Low Density Parity Check (LDPC) and other block codes are presented. An efficient and systematic method for designing partially parallel encoders is presented. A parallelism factor is selected such that the end result for the encoder is similar to the partially parallel G matrix multiplication method. In addition to the method an initial circuit is given for the G matrix multiplication encoder and the RU encoder. A circuit for the hybrid encoder is presented which achieves less power consumption and smaller area than an equivalent encoder based on the G matrix multiplication with a smaller critical path than previous encoders.

Abstract: True bit level decoding of TTCM (Turbo Trellis Coded Modulation) of variable rates and signal constellations. A decoding approach is presented that allows for decoding on a bit level basis that allows for discrimination of the individual bits of a symbol. Whereas prior art approaches typically perform decoding on a symbol level basis, this decoding approach allows for an improved approach in which the hard decisions/best estimates may be made individually for each of the individual bits of an information symbol. In addition, the decoding approach allows for a reduction in the total number of calculations that need to be performed as well as the total number of values that need to be stored during the iterative decoding. The bit level decoding approach is also able to decode a signal whose code rate and/or signal constellation type (and mapping) may vary on a symbol by symbol basis.

Abstract: This invention provides an iterative PCZZ data decoder that includes circuitry for utilizing all extrinsic information during iterative decoding by updating likelihood information for parity bits LPi, i=1, . . . , M during iterations. The extrinsic information for the parity bits is included in iterations by re-calculating soft values for parity bits LPi(k) for each iteration k. In one embodiment the parity bit soft values are re-calculated in a plurality of circuit blocks following Max-Log-APP (MLA) decoder blocks, based on soft values for data bits LDi(k). In another embodiment the parity bit soft values are re-calculated recursively within the plurality of MLA decoders. The decoder operates to control the convergence of the decoder by monitoring a soft value of one parity check symbol, e.g., L(k?1)[p(IM)], where p(IM) represents the last parity check bit in an I×M parity check array.

Abstract: An array of non-volatile memory cells includes a row with N cells and M cells. In a partial-storage step, a datum is stored in a first portion of the N cells of the row. A second portion of the N cells of the row are in an “erase” state. A first error correction code associated with the datum is stored in the M cells along with a first enable bit or guard-cell which is indicative of whether the first error correction code is active. The number of M cells, adjacent to the N cells of the row, is defined on the basis of the number N of cells. In the event the datum stored in the first portion of the N cells of the row is subsequently updated or manipulated, a second error correction code associated with the updated or manipulated datum is determined and stored in the second portion of the N cells of the row along with a second guard-cell which is indicative of whether the second error correction code is active.

Abstract: An encoder divides the data in which sector data is adjacently connected to a first RS parity generated in Reed Solomon encoding into blocks to and subjects each of the blocks to cyclic Hamming encoding so as to generate Hamming parities. Subsequently, the data in which the Hamming parities are aligned in a row is subjected to Reed Solomon encoding so as to generate a second RS parity, and encoded data in which the first RS parity and the second RS parity are adjacently connected to the sector data is output. A decoder s divides the sector data and the first RS parity into n blockes and cyclic Hamming encoding, aligns the parities thereof, corrects errors in the parities by Reed Solomon decoding by the second RS parity, then corrects 1-bit errors in blockes by cyclic Hamming decoding, and further corrects errors of 2 or more bits by Reed Solomon decoding by the first RS parity.

Abstract: An ECC circuit (103) is located between I/O terminals (1040-1047) and page buffers (1020-1027). The ECC circuit (103) includes a coder configured to generate check bits (ECC) for error correcting and attach the check bits to data to be written into a plurality of memory cell areas (1010-1017), and a decoder configured to employ the generated check bits (ECC) for error correcting the data read out from the memory cell areas (1010-1017). The ECC circuit (103) allocates a set of 40 check bits (ECC) to an information bit length of 4224=528×8 to execute coding and decoding by parallel processing 8-bit data, where data of 528 bits is defined as a unit to be written into and read out from one memory cell area (101j).

Abstract: In an encoder for encoding symbols of data using a computing device having memory constraints, a method of performing a transformation comprising loading a source block into memory of the computing device, performing an intermediate transformation of less than all of the source block, then replacing a part of the source block with intermediate results in the memory and then completing the transformation such that output symbols stored in the memory form a set of encoded symbols. A decoder can perform decoding steps in an order that allows for use of substantially the same memory for storing the received data and the decoded source block, performing as in-place transformations. Using an in-place transformation, a large portion of memory set aside for received data can be overwritten as that received data is transformed into decoded source data without requiring a similar sized large portion of memory for the decoded source data.