Abstract: Fabrication method and semiconductor device are provided. The method includes: providing a base substrate including a first region and a second region adjacent to the first region, with first fins disposed on the base substrate in the first region and on the base substrate in the second region, and initial openings disposed between adjacent first fins; forming sidewall spacers on sidewalls of the first fins to form openings from the initial openings; and forming the second fins in the openings of the second region.

Abstract: A semiconductor device includes a substrate having first and second active regions, first and second active patterns on the first and second active regions, first and second gate electrodes running across the first and second active patterns, and a high-k dielectric layer between the first active pattern and the first gate electrode and between the second active pattern and the second gate electrode. The first gate electrode includes a work function metal pattern and an electrode pattern. The second gate electrode includes a first work function metal pattern, a second work function metal pattern, and an electrode pattern. The first work function metal pattern contains the same impurity as that of the high-k dielectric layer. An impurity concentration of the first work function metal pattern of the second gate electrode is greater than that of the work function metal pattern of the first gate electrode.

Abstract: There is provided a semiconductor device including: a first wiring; a second wiring; a dielectric layer configured to insulate the first wiring and the second wiring from each other; and an impedance adjustment layer formed between the first wiring and the second wiring, and configured to adjust an impedance between the first wiring and the second wiring.

Abstract: An OLED device includes a substrate, a first active layer, a first gate electrode, a second gate electrode, first source and first drain electrodes, a first high dielectric constant (high-k) insulation structure, and a light emitting structure. The substrate has a first region and a second region. The first active layer is disposed in the first region on the substrate. The first gate electrode is disposed on the first active layer, and has a first thickness. The second gate electrode is disposed on the first gate electrode. The first source electrode and first drain electrode are disposed on the second gate electrode, and constitutes a first semiconductor element together with the first active layer and the first gate electrode. The first high-k insulation structure is disposed between the first gate electrode and the second gate electrode, and is spaced apart from the first source electrode and first drain electrode.

Abstract: An image sensor includes a substrate including a plurality of pixel regions and one or more pairs of dummy pixel regions; a pixel separation structure between two adjacent pixel regions among the plurality of pixel regions and including a first conductive layer; a dummy pixel separation structure between the one or more pairs of dummy pixel regions, electrically connected to the pixel separation structure, and including a second conductive layer; and a pixel separation contact disposed on the dummy pixel separation structure.

Abstract: Methods/structures of forming thin film resistors using interconnect liner materials are described. Those methods/structures may include forming a first liner in a first trench, wherein the first trench is disposed in a dielectric layer that is disposed on a substrate. Forming a second liner in a second trench, wherein the second trench is adjacent the first trench, forming an interconnect material on the first liner in the first trench, adjusting a resistance value of the second liner, forming a first contact structure on a top surface of the interconnect material, and forming a second contact structure on the second liner.

Abstract: Provided is a semiconductor device including a semiconductor substrate having a drift region; a transistor portion having a collector region; a diode portion having a cathode region; and a boundary portion arranged between the transistor portion and the diode portion at an upper surface of the semiconductor substrate, and having the collector region, wherein the mesa portion of each of the transistor portion and the boundary portion has an emitter region and a base region, the base region has a channel portion, and a density in the upper surface of the mesa portion in the region in which the channel portion is projected onto the upper surface of the mesa portion of the boundary portion may be smaller than the density of the region in which the channel portion is projected onto the upper surface of the mesa portion of the transistor portion.

Abstract: In one aspect, a method of forming a silicon-insulator layer is provided. The method includes arranging a silicon structure in a plasma etch process chamber and applying a plasma to the silicon structure in the plasma etch process chamber at a temperature of the silicon structure equal to or below 100° C. The plasma includes a component and a halogen derivate, thereby forming the silicon-insulator layer. The silicon-insulator layer includes silicon and the component. In another aspect, a semiconductor device is provided having a silicon-insulator layer formed by the method.

Abstract: A semiconductor package includes: a connection structure having first and second surfaces opposing each other and including a redistribution layer; a semiconductor chip disposed on the first surface of the connection structure and having connection pads connected to the redistribution layer; an encapsulant disposed on the first surface of the connection structure, encapsulating the semiconductor chip, and including an opaque or translucent resin; a mark indicating identification information and carved in the encapsulant; and a passivation layer disposed on the encapsulant and including a transparent resin.

Abstract: A method includes forming a first dummy gate and a second dummy gate over a fin that protrudes above a substrate; replacing the first dummy gate and the second dummy gate with a first metal gate and a second metal gate, respectively; forming a dielectric cut pattern between the first and the second metal gates, the dielectric cut pattern extending further from the substrate than the first and the second metal gates; forming a patterned mask layer over the first metal gate, the second metal gate, and the dielectric cut pattern, an opening in the patterned mask layer exposing a portion of the first metal gate, a portion of the second metal gate, and a portion of the dielectric cut pattern underlying the opening; filling the opening with a first electrically conductive material; and recessing the first electrically conductive material below an upper surface of the dielectric cut pattern.

Abstract: A structure with micro device includes a substrate, at least one micro device, and at least one holding structure. The micro device includes an epitaxial structure and an overcoat layer. The epitaxial structure has a top surface and a bottom surface opposite to each other and a peripheral surface connecting the top surface and the bottom surface. The overcoat layer includes a contact portion and an extension portion. The contact portion covers the peripheral surface and the bottom surface of the epitaxial structure. The extension portion connects the contact portion and extends in a direction away from the peripheral surface. The holding structure includes at least one connecting portion, at least one sacrificial portion and at least one holding portion. The connecting portion is disposed on the top surface of the epitaxial structure and the extension portion of the overcoat layer. The sacrificial portion connects the connecting portion and the holding portion.

Abstract: In some examples, an integrated circuit comprises a substrate; a first metal layer and a second metal layer positioned above the substrate; a first composite dielectric layer located on the first metal layer, wherein the first composite dielectric layer comprises a first anti-reflective coating; a second composite dielectric layer positioned on the second metal layer, wherein the second composite dielectric layer comprises a second anti-reflective coating; and a capacitor metal layer disposed over the first composite dielectric layer.

Abstract: A semiconductor package includes a first wafer, a second wafer, and an interconnect. The first wafer includes a first die, a first encapsulating material encapsulating the first die, and a first redistribution structure disposed over the first die and the first encapsulating material. The second wafer includes a second die, a second encapsulating material encapsulating the second die, and a second redistribution structure disposed over the second die and the second encapsulating material, wherein the second redistribution structure faces the first redistribution structure. The interconnect is disposed between the first wafer and the second wafer and electrically connecting the first redistribution structure and the second redistribution structure, wherein the interconnect includes a substrate and a plurality of through vias extending through the substrate for connecting the first redistribution structure and the second redistribution structure.

Abstract: A light-emitting device includes: a plurality of first electrodes disposed according to a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, respectively; a second electrode facing the plurality of first electrodes; a first emission layer disposed in the first sub-pixel and emitting first color light; a third emission layer disposed in the third sub-pixel and emitting third color light; a fourth emission layer disposed in the fourth sub-pixel and emitting near-infrared (NIR) light having a maximum emission wavelength of about 680 nm or more; and a first layer integrated with the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel.

Abstract: An inductor is formed in an IC device packaging structure. The structure includes an encapsulating material, with a ferromagnetic core in the encapsulation material. A plurality of metal layers are provided in the encapsulation material forming an inductor coil extending around the ferromagnetic core so as to form an inductor.

Abstract: A semiconductor package includes a frame including wiring layers and having a recess portion in which a stopper layer is disposed on a bottom surface, a semiconductor chip having an active surface and an inactive surface, the inactive surface being disposed in the recess portion and facing the stopper layer, a first connection portion on the connection pad, a second connection portion on the uppermost wiring layer, a stiffener on the upper surface of the frame and surround at least a portion of the second connection portion, the stiffener being spaced apart from second connection portion, an encapsulant covering at least portions of each of the frame and the semiconductor chip, and filling at least a portion of the recess portion, and a connection structure on the frame and the semiconductor chip, and including a redistribution layer electrically connected to the first and second connection portions.

Abstract: A method of fabricating a hard mask structure is provided. According to the method, a hard mask layer is disposed over a substrate. The hard mask layer includes a lower hard mask layer disposed over the substrate and an upper hard mask layer disposed over the lower hard mask layer. The hard mask layer is patterned and the upper hard mask layer is removed by selectively etching the upper hard mask layer until reaching the lower hard mask layer to form a top portion of the hard mask structure having a first dimension. A spacer material is disposed on a sidewall of the top portion of the hard mask structure. The lower hard mask layer is removed by selectively etching the lower mask layer until reaching the substrate to form a bottom portion of the hard mask structure having a second dimension.

Abstract: A semiconductor device with high aperture ratio is provided. The semiconductor device includes a transistor and a capacitor having a pair of electrodes. An oxide semiconductor layer formed over the same insulating surface is used for a channel formation region of the transistor and one of the electrodes of the capacitor. The other electrode of the capacitor is a transparent conductive film. One electrode of the capacitor is electrically connected to a wiring formed over the insulating surface over which a source electrode or a drain electrode of the transistor is provided, and the other electrode of the capacitor is electrically connected to one of the source electrode and the drain electrode of the transistor.

Abstract: A flexible display panel, a method for manufacturing a flexible display panel and a flexible display apparatus are provided. The flexible display panel includes: a flexible substrate; a flexible display screen disposed on the flexible substrate; a protection film disposed at a side of the flexible display screen away from the flexible substrate; and a connection layer sandwiched between the flexible display screen and the protection film, and the connection layer includes at least one layer of hyperelasticity film.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate including a trench. The semiconductor device further includes a gate electrode disposed in the trench, and a gate insulating film disposed between the substrate and the gate electrode. The gate electrode includes a gate conductor and a metal element, and an effective work function of the gate electrode is less than an effective work function of the gate conductor.