Abstract: In some embodiments, an integrated circuit device includes a semiconductor substrate. An active area is disposed in the semiconductor substrate. A first guard ring is disposed in the semiconductor substrate and entirely surrounds the active area. The first guard ring has a first conductivity type. A via penetrates through the semiconductor substrate and is spaced apart from the active area such that the via is disposed outside of the first guard ring. A second guard ring is disposed in the semiconductor substrate and entirely surrounds the via and the first guard ring. The second guard ring has the first conductivity type and is disjoint from the first guard ring.

Abstract: A semiconductor device includes: a silicon substrate having a first plane with a first plane orientation; a silicon oxide layer provided on a first region of the silicon substrate; a first silicon layer provided on the silicon oxide layer, the first silicon layer having a second plane with a second plane orientation different from the first plane orientation; and a wide-bandgap compound semiconductor layer having a hexagonal crystal structure.

Abstract: A thin film transistor, a method for manufacturing a thin film transistor, an array substrate and a display apparatus are provided. The thin film transistor includes a gate, a source, a drain and an active layer provided on a base substrate, both the source and the drain are electrically connected to the active layer, at least one of the source, the drain and the gate is a light-absorbing electrode, which comprises an electrode body and a light-absorbing layer, and the light-absorbing layer is arranged at a side of the electrode body facing towards the active layer.

Abstract: A light-emitting device and a method for manufacturing the light-emitting device is disclosed. Such a light-emitting device comprises a substrate, a plurality of cells disposed on the substrate, and a plurality of semiconductor dice, wherein each of the plurality of cells accommodates at least one of the plurality of dice. Each of the plurality of cells may be filled with an encapsulant, phosphor or a mixture of an encapsulant with phosphor to control light characteristics of the light-emitting device. In an alternative aspect, cells may be filled with an encapsulant, and comprise a transparent cover coated with or filled with phosphors to control light characteristics of the light-emitting device.

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes alternately forming a plurality of first films and a plurality of second films on a substrate, and forming an opening in the first and second films. The method further includes sequentially forming a first insulator, a charge storage layer, a second insulator and a semiconductor layer on surfaces of the first and second films in the opening. The second insulator includes a silicon oxynitride film, and the silicon oxynitride film is formed using a first gas that includes silicon and a first element, a second gas that includes oxygen and nitrogen, and a third gas that includes a second element that reacts with the first element.

Abstract: A display device in an embodiment according to the present invention includes a substrate, a plurality of wirings above the insulation surface, an interlayer insulation layer covering the plurality of wirings, a light emitting element above the interlayer insulation layer, a first inorganic insulation layer covering the light emitting element, a first detection electrode extending in a first direction above the first inorganic insulation layer, an organic insulation layer above the first inorganic insulation layer covering the first detection electrode, a second detection electrode extending in a second direction intersecting the first direction above the organic insulation layer, a second inorganic insulation layer above the organic insulation layer covering the second detection electrode, a first connection wiring electrically connecting the first detection electrode and one of the plurality of wirings, and a second connection wiring electrically connecting the second detection electrode and another one of

Abstract: A display device is provided. The display device includes a substrate having a first surface and a second surface opposite to the first surface, a plurality of light-emitting units disposed on the first surface of the substrate, and a plurality of conductive structures extending into the substrate from the second surface of the substrate. The plurality of conductive structures are electrically connected to the plurality of light-emitting units.

Abstract: One or more embodiments of techniques or systems for forming a semiconductor structure are provided herein. A first metal region is formed within a first dielectric region. A cap region is formed on the first metal region. A second dielectric region is formed above the cap region and the first dielectric region. A trench opening is formed within the second dielectric region. A via opening is formed through the second dielectric region, the cap region, and within some of the first metal region by over etching. A barrier region is formed within the trench opening and the via opening. A via plug is formed within the via opening and a second metal region is formed within the trench opening. The via plug electrically connects the first metal region to the second metal region and has a tapered profile.

Abstract: A PCM cell is provided that includes a phase change memory material that is sandwiched between top and bottom electrodes which are both composed of a doped silicon germanium alloy. A doped silicon germanium alloy has good electrical conductivity, while having a lower thermal conductivity than conventional conductive materials such as TiN or W that are typically used in PCM cells. The presence of the doped silicon germanium alloy mitigates heat loss in the PCM cell thus reducing reset current and, in some embodiments, thermal cross-talk between adjacent PCM cells. Further reduction of heat loss can be obtained by providing an airgap-containing dielectric spacer laterally adjacent to the PCM cell.

Abstract: A package comprising a chip carrier, an electronic chip on the chip carrier, a clip on the electronic chip, an encapsulant at least partially encapsulating the electronic chip, and an electrically conductive vertical connection structure provided separately from the clip and electrically connecting the chip carrier with the clip.

Abstract: According to one embodiment, the p-side electrode is provided on the second semiconductor layer. The insulating film is provided on the p-side electrode. The n-side electrode includes a first portion, a second portion, and a third portion. The first portion is provided on a side face of the first semiconductor layer. The second portion is provided in the first n-side region. The third portion overlaps the p-side electrode via the insulating film and connects the first portion and the second portion to each other.

Abstract: The disclosure provides an N-type thin film transistor, including a poly-silicon layer, a gate layer, a source and a drain. The poly-silicon layer includes a channel region, a source region and a drain region at two side of the channel region. The gate layer is on the channel region, a projection of the gate layer on the poly-silicon layer partially overlaps the source region and the drain region, and a thickness of the gate layer on the source region and the drain region are smaller than a thickness of the gate layer on the channel region. The source region and the drain region both include a heavily-doping region and a lightly-doping region connected to the heavily-doping region, the source and the drain are respectively on the heavily-doping region of the source region and the drain, and respectively electrically connects to the heavily-doping region of the source region and the drain.

Abstract: A method is presented for forming a semiconductor device. The method includes forming an oxygen containing interfacial layer on a semiconductor substrate, forming a hafnium oxide layer on the interfacial layer, the hafnium oxide layer crystallizing to a non-centrosymmetric phase in a final structure, forming a first electrode containing a scavenging metal, which reduces a thickness of the interfacial layer via an oxygen scavenging reaction in the final structure, on the hafnium oxide layer, and forming a second electrode on the first electrode.

Abstract: A display apparatus includes a substrate including a display area and a peripheral area disposed outside of the display area, a plurality of wiring lines disposed in the peripheral area, and an interlayer insulating layer covering the plurality of wiring lines. The interlayer insulating layer includes an upper surface having a first concave-convex surface corresponding to the plurality of wiring lines. The display apparatus further includes a first conductive layer disposed on the interlayer insulating layer and including a second upper surface having a second concave-convex surface corresponding to the first concave-convex surface, a planarization layer disposed on the first conductive layer and having a flat upper surface, a second conductive layer disposed on the planarization layer and having a flat upper surface, and a polarization plate disposed on the second conductive layer.

Abstract: Semiconductor structures and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming a gate structure over the base substrate; forming a mask layer on a top surface of the gate structure; forming pocket regions in the base substrate at both sides of the gate structure; after forming the pocket regions, forming a first protective portion covering a top surface of the mask layer and protruding from sidewall surfaces of the gate structure; and after forming the first protective portion, forming doped source/drain regions in the base substrate and portions of the pocket regions at both sides of the gate structure.

Abstract: A method of forming a semiconductor structure includes, providing a semiconductor layer, forming an interfacial layer over the semiconductor layer, depositing a high-k dielectric layer over the interfacial layer, forming a dummy gate electrode over the high-k dielectric layer, patterning the dummy gate electrode layer, the high-k dielectric layer, and the interfacial layer, resulting in a dummy gate electrode having a width less than a width of the high-k dielectric layer, forming spacers along sidewalls of the patterned dummy gate electrode, the high-k dielectric layer, and the interfacial layer, forming source/drain features, and replacing the dummy gate electrode with a metal gate electrode to form a high-k metal gate structure.

Abstract: An optical sensor includes a semiconductor substrate having a first conductive type. The optical sensor further includes a photodiode disposed on the semiconductor substrate and a metal layer. The photodiode includes a first semiconductor layer having the first conductive type and a second semiconductor layer, formed on the first semiconductor layer, including a plurality of cathodes having a second conductive type. The first semiconductor layer is configured to collect photocurrent upon reception of incident light. The cathodes are configured to be electrically connected to the first semiconductor layer and the second semiconductor layer is configured to, based on the collected photocurrent, to track the incident light. The metal layer further includes a pinhole configured to collimate the incident light, and the plurality of cathodes form a rotational symmetry of order n with respect to an axis of the pinhole.

Abstract: Disclosed is a preform for semiconductor encapsulation, mainly containing a metal or alloy, the metal or alloy further containing Sn or Sn alloy, and, Cu or Cu alloy, and still further containing at least 2% by weight of an intermetallic compound of Cu and Sn.

Abstract: A display panel and a display device are provided. The display panel includes a display region, at least one notch, and a non-display region surrounding the display region. The display region includes an irregularly-shaped edge. The at least one notch is formed by recessing the irregularly-shaped edge toward an inside of the display region. The display panel also includes an array layer disposed on a side of a base substrate. The array layer includes at least one inorganic layer, the at least one inorganic layer including at least one protruded portion. In addition, the display panel includes a display function layer disposed on a side of the array layer away from the base substrate. Further, the display panel includes at least one blocking part formed in the non-display region. The at least one blocking part is disposed around the display region and around the display function layer.

Abstract: An object of this invention is to obtain a molded module with which improvements are achieved in the packaging ability and heat dissipation performance of an inverter module itself, and in the mounting capacity of a peripheral mounting component such as a substrate, which must be taken into consideration in relation to the shape of the module. Provided is a molded module for use in power electronics, having an inbuilt semiconductor element used to supply and control a large amount of power, the molded module including at least one semiconductor switching element provided in the module and a lead frame that dissipates heat from the switching element and electrically connects an element packaged in the module to an external circuit, wherein at least one end of the module is molded in a curved shape or a polygonal shape.