Patents Examined by Su C. Kim
  • Patent number: 10593542
    Abstract: According to an embodiment, a manufacturing method of a semiconductor device includes: carrying a substrate alternately stacked an electrode layer and an insulation layer into a chamber; increasing the temperature in the chamber to a predetermined temperature; and supplying hydrogen and material gas including metal simultaneously into the chamber, and supplying oxidizing gas the partial pressure ratio of which to the hydrogen is set so as to provide an atmosphere of reducing the electrode layer, by using an ALD method, and thereby forming, on a surface of the electrode layer and a surface of the insulation layer, a metal oxide layer obtained by oxidizing the metal.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: March 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi Furuhashi, Masayuki Tanaka, Shinji Mori, Kenichiro Toratani
  • Patent number: 10586856
    Abstract: A semiconductor device is described. The semiconductor device includes a nanosheet stack including a sacrificial nanosheet oriented substantially parallelly to a substrate and a channel nanosheet disposed on the sacrificial nanosheet. The semiconductor device includes a gate formed in a direction orthogonal to the plane of the nanosheet stack, with a gate spacer positioned along a sidewall of the gate. The semiconductor device includes an inner spacer liner deposited around the nanosheet stack and the gate spacer. A first etching of the inner spacer liner is configured to produce an outer profile of the inner spacer liner, the outer profile having a substantially flat side section relative to an edge of the channel nanosheet. A second etching of the inner spacer liner is configured to remove substantially all material of the inner spacer liner from the edge of the channel nanosheet.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicolas Loubet, Julien Frougier, Wenyu Xu, Zhenxing Bi
  • Patent number: 10566365
    Abstract: An image sensor includes a sensing layer, a first microlens, and a number of second microlenses. The first microlens is disposed on the sensing layer. The second microlenses are disposed on the sensing layer adjacent to the first microlens. The diameter of the first microlens is greater than the diameter of each of the second microlenses.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: February 18, 2020
    Assignee: VISERA TECHNOLOGIES COMPANY LIMITED
    Inventors: Li-Wei Chen, Chi-Han Lin, Zong-Ru Tu
  • Patent number: 10544039
    Abstract: Methods for depositing a measured amount of a species in a sealed cavity. In one example, a method for depositing molecules in a sealed cavity includes depositing a selected number of microcapsules in a cavity. Each of the microcapsules contains a predetermined amount of a first fluid. The cavity is sealed after the microcapsules are deposited. After the cavity is sealed the microcapsules are ruptured to release molecules of the first fluid into the cavity.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: January 28, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Benjamin Stassen Cook, Kurt Wachtler, Adam Joseph Fruehling, Juan Alejandro Herbsommer, Simon Joshua Jacobs
  • Patent number: 10546746
    Abstract: A process of growing a barrier layer made of AlGaN on a GaN channel layer is disclosed. The process includes steps of, growing the GaN channel layer, growing the AlGaN barrier layer, and growing a cap layer made of GaN. The growth temperature of the AlGaN barrier layer monotonically lowers from the initial temperature, which may be equal to the growth temperature for the GaN channel layer, to the finish temperature that is lower than the initial temperature and may be substantially equal to the growth temperature of the GaN cap layer.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: January 28, 2020
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Hajime Matsuda
  • Patent number: 10515972
    Abstract: Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: December 24, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Fatma Arzum Simsek-Ege, Krishna K. Parat, Luan C. Tran, Meng-Wei Kuo, Yushi Hu
  • Patent number: 10516062
    Abstract: In a semiconductor device including a transistor including a gate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the oxide semiconductor film has an amorphous structure or a microcrystalline structure, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: December 24, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Yukinori Shima, Hajime Tokunaga, Toshinari Sasaki, Keisuke Murayama, Daisuke Matsubayashi
  • Patent number: 10504965
    Abstract: Solid-state imaging devices, electronic apparatuses, and methods of forming image sensors are provided. A solid-state imaging device or an electronic apparatus incorporating a solid-state imaging device can include a substrate and at least a first photoelectric conversion element formed in the substrate. In addition, a region with a low dielectric constant is formed. The region can include a locally thin region formed in the substrate. An insulating film is at the first side of the substrate. Where the region includes a locally thin region, the interlayer insulating film can extend into that locally thin region. A first electrode is at a side of the interlayer insulating film opposite the substrate. The device further includes a second electrode, and a photoelectric conversion layer at least partially between the first electrode and the second electrode.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: December 10, 2019
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Tetsuji Yamaguchi, Satoshi Keino
  • Patent number: 10490663
    Abstract: The present disclosure provides N-type fin field-effect transistors. An N-type fin field-effect transistor includes a semiconductor substrate; at least one fin having a first side surface and a second side surface formed over the semiconductor substrate; a gate structure crossing over the fin and formed over the semiconductor substrate; and a source region and a drain region respectively formed on top of the fin at two sides of the gate structure by an ion implantation process on one of the first side surface and the second side surface of the fin at two sides of the gate structure and a thermal annealing process to diffuse doping ions into the other of the first side surface and the second side surface of the fin.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: November 26, 2019
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Yong Li
  • Patent number: 10475824
    Abstract: The present disclosure provides a display panel, its manufacturing method and a display device. The manufacturing method of the display panel comprises: forming, on a substrate, a thin film transistor comprising a gate electrode, an active layer, a source electrode and a drain electrode; forming a hydrogen diffusion barrier layer that covers the entire substrate, wherein the hydrogen diffusion barrier layer is electrically conductive and is electrically connected to the drain electrode; and forming a photosensitive structure layer on the hydrogen diffusion barrier layer.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: November 12, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Qingrong Ren, Woobong Lee, Fengchao Wang, Jianming Sun, Yingwei Liu, Wei Yang, Dongsheng Li
  • Patent number: 10468482
    Abstract: A method includes forming a crown structure over a substrate; forming fins in the crown structure; forming an intra-device isolation region between the fins and forming inter-device isolation regions on opposing sides of the crown structure; forming a gate structure over the fins; forming a dielectric layer that extends continuously over the inter-device isolation regions, the fins and the intra-device isolation region; performing an etching process to reduce a thickness of the dielectric layer, where after the etching process, upper surfaces of the inter-device isolation regions and upper surfaces of the fins are exposed while an upper surface of the intra-device isolation region is covered by a remaining portion of the dielectric layer; and forming an epitaxial structure over the exposed upper surfaces of the fins, where after the epitaxial structure is formed, there is a void between the epitaxial structure and the intra-device isolation region.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: November 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Ru Lee, Chii-Horng Li, Chien-I Kuo, Heng-Wen Ting, Jung-Chi Tai, Li-Li Su, Tzu-Ching Lin
  • Patent number: 10468376
    Abstract: Disclosed is a semiconductor device that includes a semiconductor chip; bonding pads provided to the semiconductor chip; a plurality of lead terminals arranged around the semiconductor chip; a plurality of bonding wires that electrically connect the semiconductor chip with the plurality of lead terminals; and a resin encapsulant which encapsulates the semiconductor chip and the bonding wires, the semiconductor device further having an insulating material interposed at the interface between the bonding wires and the resin encapsulant, and the insulating material containing a nanometer-sized insulating particle and amorphous silica.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: November 5, 2019
    Assignee: Napra Co., Ltd.
    Inventor: Shigenobu Sekine
  • Patent number: 10461101
    Abstract: A semiconductor device with high aperture ratio is provided. The semiconductor device includes a transistor and a capacitor having a pair of electrodes. An oxide semiconductor layer formed over the same insulating surface is used for a channel formation region of the transistor and one of the electrodes of the capacitor. The other electrode of the capacitor is a transparent conductive film. One electrode of the capacitor is electrically connected to a wiring formed over the insulating surface over which a source electrode or a drain electrode of the transistor is provided, and the other electrode of the capacitor is electrically connected to one of the source electrode and the drain electrode of the transistor.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: October 29, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yuta Endo
  • Patent number: 10461134
    Abstract: A technique of manufacturing a display device with high productivity is provided. In addition, a high-definition display device with high color purity is provided. By adjusting the optical path length between an electrode having a reflective property and a light-emitting layer by the central wavelength of a wavelength range of light passing through a color filter layer, the high-definition display device with high color purity is provided without performing selective deposition of light-emitting layers. In a light-emitting element, a plurality of light-emitting layers emitting light of different colors are stacked. The closer the light-emitting layer is positioned to the electrode having a reflective property, the shorter the wavelength of light emitted from the light-emitting layer is.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: October 29, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Seo, Toshiki Sasaki, Nobuharu Ohsawa, Takahiro Ushikubo, Shunpei Yamazaki
  • Patent number: 10461092
    Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; a stacked body having a plurality of first insulating layers and conductive layers stacked alternately on the semiconductor substrate; a columnar semiconductor layer contacting the semiconductor substrate in the stacked body being provided extending in a stacking direction of the stacked body and including a first portion and a second portion which is provided above the first portion; a memory layer provided on a side surface of the columnar semiconductor layer facing the stacked conductive layers and extending along the columnar semiconductor layer; and a second insulating layer provided between one of the first insulating layer and the conductive layers of the stacked body.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: October 29, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Shinya Arai
  • Patent number: 10446634
    Abstract: The present disclosure discloses a flexible display panel and a flexible display device. The flexible display panel includes a first flexible substrate, a buffer layer, a display function layer, and a conduction function layer. The buffer layer and the display function layer are placed on a first side of the first flexible substrate. The conduction function layer is placed between the first flexible substrate and the display function layer, and is connected to a constant potential through a through-hole or by an end portion of the conduction function layer. By arranging the conduction function layer and connecting to the constant potential, an external interference signal from a back side of the substrate can be effectively shielded, and the conduction function layer can also serve as a blocking layer.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: October 15, 2019
    Assignee: TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Xu Qian, Wenxin Jiang, Yuan Li
  • Patent number: 10446709
    Abstract: An optical sensor is installed in a device, and includes a light-emitting element, and a light-receiving element for receiving light emitted from the light-emitting element and traveling through a space. The optical sensor detects an object present in the space, based on a change of the light impinging upon the object. A first optical waveguide is connected to the light-emitting element so as to be capable of light propagation. The first optical waveguide has a front end portion serving as a light exit portion for exiting light emitted from the light-emitting element. A second optical waveguide is connected to the light-receiving element so as to be capable of light propagation. The second optical waveguide has a front end portion serving as a light entrance portion for receiving light exiting from the light exit portion of the first optical waveguide and traveling through the space.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: October 15, 2019
    Assignee: NITTO DENKO CORPORATION
    Inventors: Naoyuki Tanaka, Yasuto Ishimaru, Yuichi Tsujita
  • Patent number: 10446583
    Abstract: To provide a semiconductor device that is not easily damaged by ESD in a manufacturing process thereof. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided to overlap with a dicing line. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided around the semiconductor device such as a transistor. The layer may be in a floating state or may be supplied with a specific potential.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: October 15, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kiyoshi Kato, Yuto Yakubo, Shuhei Nagatsuka
  • Patent number: 10435794
    Abstract: There is provided an etching method of a semiconductor substrate that includes a first layer containing germanium (Ge) and a second layer containing at least one specific metal element selected from nickel platinum (NiPt), titanium (Ti), nickel (Ni), and cobalt (Co), the method including: bringing an etching solution which contains a non-halogen acidic compound into contact with the second layer and selectively removing the second layer.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: October 8, 2019
    Assignee: FUJIFILM Corporation
    Inventors: Naotsugu Muro, Tetsuya Kamimura, Satomi Takahashi, Akiko Koyama, Atsushi Mizutani
  • Patent number: 10410872
    Abstract: Implementations described herein generally relate to the fabrication of integrated circuits and particularly to the deposition of a boron-doped amorphous silicon layers on a semiconductor substrate. In one implementation, a method of forming a boron-doped amorphous silicon layer on a substrate is provided.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: September 10, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Rui Cheng, Ziqing Duan, Milind Gadre, Praket P. Jha, Abhijit Basu Mallick, Deenesh Padhi