Abstract: A method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires.

Abstract: A chip package process includes the following steps. A supporting structure and a carrier plate are provided. The supporting structure has a plurality of openings. The supporting structure is disposed on the carrier plate. A plurality of chips is disposed on the carrier plate. The chips are respectively located in the openings of the supporting structure. An encapsulated material is formed to cover the supporting structure and the chips. The supporting structure and the chips are located between the encapsulated material and the carrier plate. The encapsulated material is filled between the openings and the chips. The carrier plate is removed. A redistribution structure is disposed on the supporting structure, wherein the redistribution structure is connected to the chips.

Abstract: An insulating film provided between adjacent pixels is referred to as a bank, a partition, a barrier, an embankment or the like, and is provided above a source wiring or a drain wiring for a thin film transistor, or a power supply line. In particular, at an intersection portion of these wirings provided in different layers, a larger step is formed there than in other portions. Even when the insulating film provided between adjacent pixels is formed by a coating method, thin portions are problematically partially formed due to this step and the withstand pressure is reduced. In the present invention, a dummy material is arranged near the large step portion, particularly, around the intersection portion of wirings, so as to alleviate unevenness formed thereover. The upper wiring and the lower wiring are arranged in a misaligned manner so as not to align the end portions.

Abstract: Provided is a flexible organic light-emitting diode display. The flexible organic light-emitting diode display includes a flexible substrate, a unit pixel and an anti-reflection layer. The unit pixel is disposed on the flexible substrate and includes an emission area and a non-emission area. The anti-reflection layer is disposed to correspond to the emission area except the non-emission area.

Abstract: A display device includes a first substrate, a first active element layer, first to third light-emitting elements, a first pixel defining layer, and fourth to sixth light-emitting elements. The first active element layer is disposed on the first substrate. The first, second and third light-emitting elements are electrically connected with the first active element layer. The first, second and third light-emitting elements have first, second and third light-emitting layers respectively. The first pixel defining layer is disposed on the first active element layer and has first, second and third openings. The first, second and third light-emitting layers are disposed in the first, second and third openings respectively. The fourth, fifth and sixth light-emitting elements are disposed on the first pixel defining layer. A vertical distance between the first light-emitting element and the fourth light-emitting element is greater than 0 micrometers and less than or equal to 5 micrometers.

Abstract: A sensor includes a substrate, an electrode, a deformable membrane, and a compensating structure. The substrate includes a first side and a second side. The first side is opposite to the second side. The substrate comprises a cavity on the first side. The electrode is positioned at a bottom of the cavity on the first side of the substrate. The deformable membrane is positioned on the first side of the substrate. The deformable membrane encloses the cavity and deforms responsive to external stimuli. The compensation structure is connected to outer periphery of the deformable membrane. The compensation structure creates a bending force that is opposite to a bending force of the deformable membrane responsive to temperature changes and thermal coefficient mismatch.

Abstract: A technique of manufacturing a display device with high productivity is provided. In addition, a high-definition display device with high color purity is provided. By adjusting the optical path length between an electrode having a reflective property and a light-emitting layer by the central wavelength of a wavelength range of light passing through a color filter layer, the high-definition display device with high color purity is provided without performing selective deposition of light-emitting layers. In a light-emitting element, a plurality of light-emitting layers emitting light of different colors are stacked. The closer the light-emitting layer is positioned to the electrode having a reflective property, the shorter the wavelength of light emitted from the light-emitting layer is.

Abstract: In a method for processing a substrate, a conductive cap layer is selectively formed over a plurality of conductive structures that are positioned in a first dielectric layer. A second dielectric layer is selectively formed over the first dielectric layer. A third dielectric layer is selectively formed over the second dielectric layer. A fourth dielectric layer is then formed over the plurality of conductive structures and the third dielectric layer, and an interconnect structure is subsequently formed within the fourth dielectric layer. The interconnect structure includes a via structure that has a first portion positioned over the conductive cap layer so that sidewalls of the first portion are surrounded by the third dielectric layer, and a second portion disposed over the first portion and the third dielectric layer.

Abstract: A light emitting element includes a semiconductor layered body, an insulating film, first and second electrodes, and first and second external connection parts. The first semiconductor layer is exposed from the light emitting layer and the second semiconductor layer at exposed portions arranged in columns each extending in a first direction. The insulating film defines openings respectively located above the exposed portions. The first electrode is connected to the first semiconductor layer through the openings and covers a part of the second semiconductor layer via the insulating film. The first external connection part is connected to the first electrode and spaced apart from the exposed portions in the plan view. The first external connection part has a shape elongated in the first direction between adjacent ones of the columns of the exposed portions. The second external connection part is connected to the second semiconductor layer via the second electrode.

Abstract: A semiconductor device, includes: a first semiconductor chip including a first semiconductor substrate; and a second semiconductor chip including a second semiconductor substrate, wherein the first semiconductor substrate has a first substrate main surface and a first substrate back surface facing opposite directions in a first direction, and includes a first region and a second region disposed on the first substrate main surface, wherein the first semiconductor chip includes: a first MOSFET of a first type structure formed to include the first region; and a control circuit formed to include the second region, wherein the second semiconductor chip includes a second MOSFET of a second type structure formed to include the second semiconductor substrate, and wherein the second type structure is different from the first type structure.

Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; a stacked body having a plurality of first insulating layers and conductive layers stacked alternately on the semiconductor substrate; a columnar semiconductor layer contacting the semiconductor substrate in the stacked body being provided extending in a stacking direction of the stacked body and including a first portion and a second portion which is provided above the first portion; a memory layer provided on a side surface of the columnar semiconductor layer facing the stacked conductive layers and extending along the columnar semiconductor layer; and a second insulating layer provided between one of the first insulating layer and the conductive layers of the stacked body.

Abstract: A method includes forming a crown structure over a substrate; forming fins in the crown structure; forming an intra-device isolation region between the fins and forming inter-device isolation regions on opposing sides of the crown structure; forming a gate structure over the fins; forming a dielectric layer that extends continuously over the inter-device isolation regions, the fins and the intra-device isolation region; performing an etching process to reduce a thickness of the dielectric layer, where after the etching process, upper surfaces of the inter-device isolation regions and upper surfaces of the fins are exposed while an upper surface of the intra-device isolation region is covered by a remaining portion of the dielectric layer; and forming an epitaxial structure over the exposed upper surfaces of the fins, where after the epitaxial structure is formed, there is a void between the epitaxial structure and the intra-device isolation region.

Abstract: A method for fabricating calcite channels in a nanofluidic device is described. A photoresist is coated on a substrate, and a portion of the photoresist is then exposed to a beam of electrons in a channel pattern. The exposed portion of the photoresist is developed to form a channel pattern, and calcite is deposited in the channel pattern using a calcite precursor gas. The deposited calcite includes at least one side having a length in a range of approximately 50 to 100 nanometers. The photoresist remaining after developing the exposed portion of the photoresist is removed.

Abstract: Methods of fabricating a solar cell including metallization techniques and resulting solar cells, are described. In an example, a semiconductor region can be formed in or above a substrate. A first metal layer can be formed over the semiconductor region. A laser can be applied over a first region of the metal layer to form a first metal weld between the metal layer and the semiconductor region, where applying a laser over the first region comprises applying the laser at a first scanning speed. Subsequent to applying the laser over the first region, the laser can be applied over a second region of the metal layer where applying the laser over the second region includes applying a laser at a second scanning speed. Subsequent to applying the laser over the second region, the laser can be applied over a third region of the metal layer to form a second metal weld, where applying the laser over the third region comprises applying the laser at a third scanning speed.

Abstract: A semiconductor device comprises a substrate, a gate structure disposed on the substrate and a gate dielectric layer disposed between the substrate and the gate structure. The gate structure has a first sidewall and a second sidewall opposite to the first sidewall. A first insulating layer disposed on the gate dielectric layer and on the first sidewall of the gate structure. The first insulating layer has a first bird's beak portion covering a rounded bottom corner of the gate structure. A pair of spacers are disposed on the first insulating layer and on the second sidewall, respectively.

Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a base substrate, and forming a first stress layer in the base substrate. The method also includes forming a gate structure on the base substrate. The first stress layer in the base substrate is on both sides of the gate structure. In addition, the method includes after forming the gate structure, forming an opening in the first stress layer by back-etching the first stress layer. Further, the method includes forming a second stress layer in the opening of the first stress layer.

Abstract: A method for fabricating a semiconductor device having a substantially undoped channel region includes performing an ion implantation into a substrate, depositing a first epitaxial layer over the substrate, and depositing a second epitaxial layer over the first epitaxial layer. In various examples, a plurality of fins is formed extending from the substrate. Each of the plurality of fins includes a portion of the ion implanted substrate, a portion of the first epitaxial layer, and a portion of the second epitaxial layer. In some embodiments, the portion of the second epitaxial layer of each of the plurality of fins includes an undoped channel region. In various embodiments, the portion of the first epitaxial layer of each of the plurality of fins is oxidized.

Abstract: A method is presented for integrating an electronic component in back end of the line (BEOL) processing. The method includes forming a first electrode over a semiconductor substrate, forming a first electrically conductive material over a portion of the first electrode, forming a second electrically conductive material over the first electrically conductive material, where the first and second electrically conductive materials define a p-n junction, depositing a phase change material over the p-n junction, and forming a second electrode over the phase change material.

Abstract: In a general aspect, a method can include forming a first pillar of a first conductivity type and a second pillar of a second conductivity type, alternately disposed with the first pillar. The second pillar can be in direct contact with the first pillar. The method can also include forming an implant of the second conductivity type in an upper portion of the second pillar. The implant can have a doping concentration that is higher than a doping concentration of a lower portion of the second pillar. The method can further include forming a Schottky metal layer having a first portion directly disposed on an upper surface of the first pillar and a second portion directly disposed on the implant along an upper surface of the second pillar. The first portion of the Schottky metal layer can be wider than the second portion of the Schottky metal layer.

Abstract: An package structure includes a substrate, a pair of electrodes and a solder pad layer both electrically connected to each other and respectively disposed on two opposite surfaces of the substrate, a lighting diode arranged above the substrate and electrically connected to the pair of electrodes, a wall disposed on the substrate and arranged around the lighting diode, and a package compound disposed inside of the wall and covering the lighting diode. The package compound includes an attaching portion disposed on a top surface of the lighting diode, and a surrounding portion arranged around the attaching portion. The surrounding portion has an annular slot arranged on a top surface thereof. A bottom end of the annular slot is located at a position aligning with 25%˜90% of a thickness of the lighting diode along a height direction.