Abstract: Provided is a three-dimensional integrated circuit (3DIC) structure including a first die and a second die bonded together by a hybrid bonding structure. One of the first die and the second die has a pad and a cap layer disposed over the pad. The cap layer exposes a portion of a top surface of the pad, and the portion of the top surface of the pad has a probe mark. A bonding metal layer of the hybrid bonding structure penetrates the cap layer to electrically connect to the pad. A method of fabricating the first die or the second die of 3DIC structure is also provided.

Abstract: A quantum dot light emitting diode (QLED) and a manufacture method thereof, a display panel are provided. The QLED includes a hole transport layer and a quantum dot light emitting layer, the hole transport layer includes a porous structure layer having pores, the quantum dot light emitting layer is disposed on the hole transport layer; the quantum dot light emitting layer contacts the porous structure layer, and a material of the quantum dot light emitting layer is disposed in at least a part of the pores.

Abstract: A semiconductor memory device includes a semiconductor substrate having an active region of a first conductivity type defined by a device isolation layer, a first impurity region in the active region, an anti-fuse gate electrode on the semiconductor substrate and extending across the first impurity region, an anti-fuse gate dielectric layer between the anti-fuse gate electrode and the first impurity region, a selection gate electrode on the semiconductor substrate and extending across the active region, a selection gate dielectric layer between the selection gate electrode and the active region, and a second impurity region in the active region between the selection gate electrode and the anti-fuse gate electrode. The first and second impurity regions have impurities of a second conductivity type. The first impurity region has an impurity concentration less than the impurity concentration of the second impurity region.

Abstract: An organic EL display panel including pixel electrodes above a substrate in a matrix, column banks above the substrate at least between edges of the pixel electrodes in a row direction, extending in a column direction and side-by-side in the row direction, organic light emitting layers continuous in the column direction in gaps between the column banks, and a counter electrode layer above the organic light emitting layers. Width in the row direction of the organic light emitting layers, which is defined by width of the gaps between the column banks, changes at intervals in the column direction. For each of the light emitting layers, a minimum interval is equal to or less than a pitch in the column direction of the pixel electrodes and the changes are different from others of the light emitting layers.

Abstract: Embodiments of the present disclosure are directed towards techniques to provide a memory device with reduced capacitance. In one embodiment, a memory array is formed in a die, and includes one or more pillars and a plurality of wordlines coupled with the one or more pillars. Adjacent wordlines of the plurality of wordlines are separated by respective dielectric layers, which may include components, to reduce capacitance of the plurality of wordlines. The components comprise air gaps or low-k dielectric material. Other embodiments may be described and/or claimed.

Abstract: An insulating film provided between adjacent pixels is referred to as a bank, a partition, a barrier, an embankment or the like, and is provided above a source wiring or a drain wiring for a thin film transistor, or a power supply line. In particular, at an intersection portion of these wirings provided in different layers, a larger step is formed there than in other portions. Even when the insulating film provided between adjacent pixels is formed by a coating method, thin portions are problematically partially formed due to this step and the withstand pressure is reduced. In the present invention, a dummy material is arranged near the large step portion, particularly, around the intersection portion of wirings, so as to alleviate unevenness formed thereover. The upper wiring and the lower wiring are arranged in a misaligned manner so as not to align the end portions.

Abstract: A chip connection method and structure are provided. The method includes: providing a first connection line and a second connection line on a substrate, wherein, in the thickness direction of the substrate, a distance between the first connection line and the chip is smaller than a distance between the second connection line and the chip; providing the chip on a top surface of the substrate, the chip being provided with at least two chip pins; and providing the substrate with a second through hole corresponding to the second connecting line and provided therein with a second conductive layer, at least one chip pin being electrically connected to the first connection line, and at least one of the remaining chip pin being corresponding to a first opening of the second through, and the second conductive layer electrically connecting the chip pin and the second connection line.

Abstract: Implementations of semiconductor packages may include: a lead frame having at least one corner lead, the at least one corner lead positioned where two edges of the package meet, and the at least one lead having a half etch on a first portion of the lead and a half etch on a second portion of the lead. The first portion may extend internally into the package to create a mechanical mold compound lock between a mold compound of the package and the lead. The second portion may be located on at least one of the two edges of the package.

Abstract: A PIN type infrared photodiode including a first electrode, a n-type semiconductor, an atomic layer deposition coating of lead sulfide, a p-type semiconductor and a second electrode, wherein the n-type semiconductor comprises nanowires conformally coated with the atomic layer deposition coating of lead sulfide.

Abstract: A semiconductor device includes a first electrode on a substrate, a second electrode on the substrate, a dielectric layer structure between the first electrode and the second electrode, and a crystallization inducing layer between the dielectric layer structure and the first electrode. The dielectric layer structure includes a first dielectric layer including a first dielectric material and a second dielectric layer on the first dielectric layer and including a second dielectric material.

Abstract: A flexible display device, which has a bending area and a non-bending area, includes a display panel, and a window member disposed on the display panel and including a first glass substrate, a second glass substrate disposed opposite to the second glass substrate, and a bonding layer disposed between the first glass substrate and the second glass substrate. The bonding layer includes a first bonding part overlapping the bending area and a second bonding part overlapping the non-bending area and having a modulus greater than a modulus of the first bonding part.

Abstract: Disclosed by the present disclosure are an organic thin film transistor structure and a manufacturing method, a gas sensor, and a related apparatus: a gap, which contacts an organic active layer and which is used for accommodating a gas to be detected, is provided in the organic thin film transistor structure.

Abstract: A chip scale packaging (CSP) light emitting diode (LED) device includes a flip-chip LED semiconductor die and a beam shaping structure (BSS) to form a monochromatic CSP LED device. A photoluminescent structure can be disposed on the LED semiconductor die to form a phosphor-converted white-light CSP LED device. The BSS is fabricated by dispersing light scattering particles with concentration equal to or less than 30% by weight into a polymer resin material, and is disposed adjacent to the edge portion of the photoluminescent structure or the LED semiconductor die; or disposed remotely above the photoluminescent structure or the LED semiconductor die. The BSS disposed at the edge portion of the device can reduce the edge-emitting light of the device; while the BSS disposed at the top portion of the device can reduce the top-emitting light of the device, therefore shaping the radiation pattern and the viewing angle of the device.

Abstract: The present disclosure provides a package structure, a manufacturing method for the same, and a display device. The package structure includes a substrate, an organic light emitting device disposed on the substrate, and an encapsulation film layer disposed above the organic light emitting device, the encapsulation film layer encapsulating the organic light emitting device onto the substrate, wherein an adsorption structure is formed in the encapsulation film layer, and the adsorption structure is configured to absorb moisture and oxygen.

Abstract: Micromachined ultrasonic transducers integrated with complementary metal oxide semiconductor (CMOS) substrates are described, as well as methods of fabricating such devices. Fabrication may involve two separate wafer bonding steps. Wafer bonding may be used to fabricate sealed cavities in a substrate. Wafer bonding may also be used to bond the substrate to another substrate, such as a CMOS wafer. At least the second wafer bonding may be performed at a low temperature.

Abstract: A three dimension Not AND (NAND) memory structure with a floating gate and a method for fabricating the same are provided. In an embodiment, a method for fabricating a 3D NAND structure includes forming a word line stack on a dielectric cap covering a semiconductor substrate. The method also includes forming a hole through the word line stack and the dielectric cap and forming a floating gate trap on a surface of the hole. The method also includes epitaxially growing a semiconductor such as silicon in the hole to form a device channel with substantially uniform grain. The method also includes forming a bit line over the channel.

Abstract: Embodiments of the invention are directed to methods of forming a FinFET. A non-limiting example method includes forming a fin across from a major surface of a substrate. A dummy gate is formed around a channel region of the fin. A source region or a drain region is formed on the fin, and the dummy gate is replaced with a metal gate structure. Subsequent to replacing the dummy gate with the metal gate structure, dopants are inserted into the source region or the drain region.

Abstract: In some embodiments, an integrated circuit device includes a semiconductor substrate. An active area is disposed in the semiconductor substrate. A first guard ring is disposed in the semiconductor substrate and entirely surrounds the active area. The first guard ring has a first conductivity type. A via penetrates through the semiconductor substrate and is spaced apart from the active area such that the via is disposed outside of the first guard ring. A second guard ring is disposed in the semiconductor substrate and entirely surrounds the via and the first guard ring. The second guard ring has the first conductivity type and is disjoint from the first guard ring.

Abstract: A semiconductor device includes: a silicon substrate having a first plane with a first plane orientation; a silicon oxide layer provided on a first region of the silicon substrate; a first silicon layer provided on the silicon oxide layer, the first silicon layer having a second plane with a second plane orientation different from the first plane orientation; and a wide-bandgap compound semiconductor layer having a hexagonal crystal structure.

Abstract: A thin film transistor, a method for manufacturing a thin film transistor, an array substrate and a display apparatus are provided. The thin film transistor includes a gate, a source, a drain and an active layer provided on a base substrate, both the source and the drain are electrically connected to the active layer, at least one of the source, the drain and the gate is a light-absorbing electrode, which comprises an electrode body and a light-absorbing layer, and the light-absorbing layer is arranged at a side of the electrode body facing towards the active layer.