Abstract: A configurable power controller and method for controlling power of a macro circuit block, such as a memory circuit, in multiple power modes is described to help minimize power consumption of the macro circuit block when the application environment for the macro circuit block is in a lower power mode than during its normal power mode.

Abstract: A driving strength control circuit and a data output circuit for controlling driving strength of a data driver based on a user's demand are provided to make it possible to control the driving strength through a fuse cutting. The driving strength control circuit includes a fuse signal generating unit for generating a fuse signal based on a fuse cutting, a select signal generating unit for generating select signals in response to the fuse signal, a driving control signal generating unit for receiving set-up signals and generate driving control signals in response to the select signals, and a driving signal generating unit for driving signals by decoding the driving control signals.

Abstract: A device monitors at least one power switch which is series-mounted with a logic core between a first and a second potential. A connection point between the switch and logic core is carried to a third potential. The switch is biased by a biasing potential. The device includes a feedback control module mounted between first and second potentials which is capable of generating a set potential representative of the third potential variation. A biasing module of the power switch is mounted between the first and second potentials, and generates a biasing potential based on the set potential. The biasing potential linearly varies with the decrease of the third potential.

Abstract: An internal voltage generator includes a pull-up driver to pull-up drive a supply terminal of an internal voltage, a pull-down driver to pull-down drive the supply terminal of the internal voltage, a pull-up driving control unit to turn on the pull-up driver when a first feedback voltage corresponding to the internal voltage becomes lower than a reference voltage, and a pull-down driving control unit to turn on the pull-down driver when a second feedback voltage becomes higher than the reference voltage, the second feedback voltage having a voltage level corresponding to that of the internal voltage and lower than that of the first feedback voltage.

Abstract: Generating a bandgap reference by generating a first current in a first circuit and a second current in a second circuit, a control circuit forcing the first and second currents to have a first magnitude proportional-to-temperature. Generating a third current in a third circuit having a second magnitude based on a first voltage associated with the first circuit, the second magnitude being complementary-to-temperature. Adding the first and second magnitudes in a fourth circuit to form a third magnitude substantially constant over change in temperature, the fourth circuit generating a fourth current having the third magnitude. Adding the first and second magnitudes to generate a fifth current having the first magnitude in a fifth circuit and a sixth current having the second magnitude in a sixth circuit, the fifth and sixth circuits sinking current from the fourth circuit.

Abstract: An integrated circuit, including: (i) a power gated circuit which power supply is shut down during a low-power period; (ii) a retention circuit, coupled to the power gated circuit during at least a portion of a non-low-power period, the retention circuit is adapted to store, during the low-power period, state information reflecting a state of the power gated circuit before the low-power period started; (iii) a first portion of the power grid, coupled to the retention circuit and to a first end of a power supply switch, adapted to provide to the retention circuit a supply voltage during the low-power period and during a non-low-power period; wherein the power supply switch is open during the low-power period and is closed during the non-low-power period; and (iv) a second portion of the power grid, coupled to a second end of the power supply switch and to the power gated circuit; adapted to supply a gated supply voltage to the power gated circuit during the non-low-power period.

Abstract: A design structure that includes at least one tunneling device voltage reference circuit for use in low voltage applications is disclosed. The tunneling device voltage reference circuit includes a pair of voltage dividing device stacks, one having a linear voltage output and the other having a non-linear voltage output. A feedback circuit supplies a regulated voltage to each of the voltage dividing stacks so that the output voltages of the two device stacks equalize. Once the feedback circuit has locked, any one of the device stack output voltages and the regulated voltage may be used as a voltage reference.

Abstract: An integrated circuit and a method for operating an integrated circuit is disclosed. One embodiment provides a semi-conductor component, an electronic system, and a method for operating an integrated circuit. A method for operating an integrated circuit provides applying a voltage to a line or a connection in accordance with data to be input. A current is applied to the line or the connection in accordance with data to be output.

Abstract: A fuse circuit of a semiconductor integrated apparatus includes first and second fuse blocks. The first fuse block includes a first up fuse block where a first plurality of fuses are arranged and a first down fuse block where a second plurality of fuses are arranged. The second plurality of fuses comprises fewer fuses than the first plurality of fuses. The second fuse block includes a second up fuse block where a third plurality of fuses are arranged, the third plurality of fuses comprising the same number of fuses as the second plurality of fuses, and a second down fuse block that includes a fourth plurality of fuses, the fourth plurality of fuses comprising the same number of fuses as the first plurality of fuses. The first up fuse block is opposite the second up fuse block and the first down fuse block is opposite the second down fuse block.

Abstract: An apparatus and a method to reduce temperature dependence of a reference voltage have been presented. In one embodiment, the method includes generating a reference voltage associated with a difference between a first threshold voltage of a first transistor and a second threshold voltage of a second transistor. The method may further include biasing the first transistor and the second transistor at a predetermined ratio of currents of the first and the second transistors to reduce temperature dependence of the reference voltage.

Abstract: A detection circuit includes a current source with no temperature coefficient; a current generation circuit that generates a VBE proportional reference current from the current source with no temperature coefficient; a current mirror circuit that returns an output current of the current generation circuit; a reference voltage generation circuit that generates a VBE proportional voltage with a negative temperature coefficient on the basis of the current returned by the current mirror circuit so that the VBE proportional voltage is used as a reference voltage of a comparator; and a full-wave rectifying means, having a differential pair and a rectifier circuit, using the current source with no temperature coefficient, having an alternating current signal supplied as an input signal, for generating a direct current voltage with a negative coefficient on the basis of a voltage obtained by full-wave rectifying the alternating current signal, and for using the generated voltage as a comparative voltage of the compar

Abstract: A switched capacitor circuit includes an amplifier, a charging unit, an offset unit, and an integrating unit. The charging unit is coupled between an input node and a first node, and is for accumulating charge corresponding to an input signal during a sampling mode. The offset unit is coupled between the first node and an input of the amplifier, and is for maintaining the first node to be a virtual ground during an integrating mode. The integrating unit is coupled between the first node and an output of the amplifier, and is for receiving charge from the charging unit during the integrating mode.

Abstract: A voltage pumping device is provided which includes a source voltage generator for generating a source voltage which has a first voltage level for a predetermined period and a second voltage level after a lapse of the predetermined period, the second voltage level being constant, and a pumping circuit configured to receive the source voltage and pump a predetermined voltage.

Abstract: In a voltage divider and an internal supply voltage generation circuit, the voltage divider includes a first transistor having a resistance value that varies in proportion to a change in temperature; and a second transistor having a resistance value that varies in inverse proportion to the change in temperature.

Abstract: A switched-capacitor charge pump comprises a two-phase charging circuit, cross-coupled transistors connected to output nodes of the switched capacitors, and a pump output connected to source terminals of the cross-coupled transistors. The charge pump has side transistors for boosting charge transfer, and gating logic of the side transistors includes level shifters which control connections to the pump output or a reference voltage. Negative and positive charge pump embodiments are provided. The charging circuit advantageously utilizes non-overlapping wide and narrow clock signals to generate multiple gating signals. The pump clock circuit preferably provides independent, programmable adjustment of the widths of the wide and narrow clock signals. An override mode can be provided using clamping circuits which shunt the pump output to the second nodes of the switched capacitors.

Abstract: A circuit (200) can include a reference circuit (202) and a start-up circuit (204). A start-up circuit (204) can include a low threshold voltage reference current device (N3) that can pull a start node (210) low in a start-up operation. This can enable activation device (P3), which can place reference circuit (202) in a stable operating mode. Operation of transistor (N3) can be essentially independent of a high power supply voltage and start-up circuit (204) can include no resistors.

Abstract: A circuit and method are given, to realize a high efficiency voltage multiplier for integrated circuits generating an internal and flexible positive or negative high voltage on-chip supply voltage from low external positive or negative supply voltages or ground. Applying multi-phase control signals to voltage boost internal nodes allows for eliminating threshold voltage drop losses and thus improves the voltage pumping gain compared to circuits with diode-configured FETs of prior art. Making use of voltage signals from antecedent stages in order to bias the bulk of MOS transistors fabricated in triple-well technology enables relaxing of the gate oxide stress within high order stage MOS transistors. Such a method, called leap-frog bulk potential tracking method, makes MOS transistors from different stages exhibit about the same body effect, which is very important because MOS transistors of higher order stages now show the same performance as MOS transistors from lower order stages.

Abstract: A biasing device can supply a bias voltage to bias-able element by coupling a bias circuit to the bias-able element, coupling a state adjusting device to the biasing circuit, configuring the state adjusting device to 1) increase an initial biasing voltage by a first amount when an intermediate voltage threshold exceeds a voltage drop across the bias-able element and 2) increment the increased initial bias voltage by a second amount, where the second amount is a fraction of the first amount, until the voltage drop across the bias-able element substantially equals a predetermined bias voltage. The bias circuit of the biasing device can include a variable resistance, which is controlled by the state adjusting device and configured to vary the biasing voltage, in series with the bias-able element.

Abstract: A trimming system for determining a trim solution for a semiconductor device includes an internal value generating circuit for generating an internal value based upon a counter value. The relationship between the internal delay value and an external reference is compared to determine if the counter value is a possible trim solution, while predetermined counter values are excluded as a trim solution.

Abstract: A two stage voltage boost circuit, IC and design structure are disclosed for boosting a supply voltage using gate control circuitry to reduce gate oxide stress, thus allowing lower voltage level FETs to be used. The voltage boost circuit may include a first stage for boosting the supply voltage to a first boosted voltage; a first passgate coupled to the first stage; a first gate control circuit for generating an on-state gate voltage level for the first passgate adjusted to reduce gate oxide voltage stress on the passgate; a second stage for boosting the first boosted voltage to a second boosted voltage; a second passgate coupled to the second stage, and a second gate control circuit for generating an on-state gate voltage level for the second passgate adjusted to reduce gate oxide voltage stress on the second passgate.