Abstract: A semiconductor integrated circuit device may include a first internal circuit operating at a first voltage higher than a power supply voltage of the device, and a second internal circuit operating at a second voltage lower than the first voltage. An interface circuit may be provided to restrict a voltage transferred from the first internal circuit to the second internal circuit. The first internal circuit may include a metal oxide semiconductor (MOS) transistor having a relatively thick gate insulation layer, and the second internal circuit may have a MOS transistor having a relatively thin gate insulation layer. The interface circuit, by restricting voltage, may reduce an electric field applied to the gate insulation layer of the second MOS transistor in an effort to prevent a reduction in turn-on speed of the second MOS transistor.

Abstract: An inter voltage generation circuit includes a pumping voltage generator to generate a pumping voltage, a level comparator to compare the pumping voltage level with a peripheral voltage level and output an enable signal depending on the comparison result, and a peripheral voltage generator to output a pumping enable signal according to the enable signal and generate a peripheral voltage according to the enable signal.

Abstract: For downsizing a charge pump circuit which selects a voltage multiple ratio, converts its input voltage and outputs the converted voltage, the number of switching devices of the charge pump circuit is reduced. The control circuit of the charge pump circuit is configured to carry out switching control for multiple switching devices and charge/discharge at least a first capacitor and a second capacitor so as to have at least a 2Vi mode for alternately repeating a first state and a second state, and a 1.5Vi mode for alternately repeating a third state and a fourth state, thereby carrying out boosting depending on the detected input voltage.

Abstract: A semiconductor integrated circuit includes a voltage generating circuit configured to generate a predetermined voltage, an NMOS transistor configured to receive at a gate node thereof the predetermined voltage generated by the voltage generating circuit, to receive at a drain node thereof an external power supply voltage, and to generate at a source node thereof a stepped-down voltage by reducing the external power supply voltage in response to the predetermined voltage, and a PMOS transistor, provided between the drain node of the NMOS transistor and the external power supply voltage, configured to receive at a gate node thereof a power-down signal indicative of a power-down mode. The predetermined voltage applied to the gate node of the NMOS transistor is set to LOW in response to a HIGH state of the power-down signal applied to the gate node of the PMOS transistor.

Abstract: The p- well back bias for NCH transistors in a DRAM sense amplifier circuit is dynamically adjusted. Preferably, during sensing, the p- well back bias for the NCH transistors of the sense amp is increased to in effect lower the threshold voltages for the NCH transistors so that they are more easily activated during sensing. The back bias voltage is preferably increased from ground (its normal value) to the threshold voltage of a NCH transistor (NVt), a value low enough to prevent the circuit from latch-up. Moreover, this voltage is preferably arrived at using a Vt detector/bias circuitry which receives the p- well bias voltage as feedback. While benefiting the disclosed sense amp circuit, the dynamic bias provided to the p- well of the NCH transistors can also benefit NCH transistors in other CMOS circuitry as well. Moreover, similar modifications to dynamically bias the n- wells of PCH transistors in CMOS circuits are also provided to increase the sensing margins of PCH transistors as well.

Abstract: A voltage comparator contains low voltage devices (e.g., bipolar or MOS transistors) and high voltage devices (e.g., DMOS transistors). The low voltage devices, which cannot sustain a voltage greater than a relatively small range of variation that is substantially less than the range of potential variation of the input voltage, are connected in a differential amplifier configuration to perform precision differential measurements on the input voltage. The high voltage devices are interconnected with the low voltage devices in a manner that enables operating levels of the low voltage devices to move up/down, or ‘slide’, with variations in the input voltage, so that the low voltage devices are effectively immune to high levels of the input voltage.

Abstract: A track-and-hold peak detector circuit, which can operate at low input signal frequencies, includes a capacitor to hold a peak voltage of the input signal and logic circuitry that reduces an effect of leakage current into or out of the capacitor, and therefore, provides protection against self-switching of an output signal of the peak detector circuit.

Abstract: A constant current circuit and a constant current generating method, wherein when a voltage in substantially no temperature dependence is applied to an element to output a constant current, temperature dependence of the element can be cancelled. A current indicative of first temperature dependence, which is generated by applying a bias voltage in substantially no temperature dependence to a first current setting section, and a current indicative of second temperature dependence, which is generated by applying a bias voltage in substantially no temperature dependence to a second current setting section are added and outputted as a constant current in substantially no temperature dependence.

Abstract: An integrated circuit comprises a gain stage circuit coupled to a compensation circuit. Both the gain stage circuit and the compensation circuit respectively comprise a first current source and a second current source that are subject to the same process variations. A negative feedback circuit is used to generate a corrective current in relation to the second current source, indicative of a current that needs to flow through a load in addition to a current flowing through the second current source in order for a variable voltage to be substantially equal to a reference voltage used to drive the first and second current sources. A compensating current corresponding to the corrective current generated for the second current source is applied to the first current source to compensate for process variation in the gain stage circuit in respect to the first current source.

Abstract: A power supply controller including a MOSFET between a power source and a load, a ground terminal, a gate driving circuit structured to control a gate potential of the MOSFET to turn on power and control the gate potential of the MOSFET to turn off power based on a ground terminal potential, and a turn-off circuit structured to switch the MOSFET into a turn-off state regardless of control by the gate driving circuit when the ground terminal potential is at a higher value than a source potential of the MOSFET.

Abstract: A device, having temperature compensation, includes a constant voltage provider for providing a constant voltage; and a compensating load coupled to the constant voltage provider for providing a resistive load to transform the constant voltage into a substantially constant current. The compensating load contains a resistor, having a negative temperature coefficient and coupled to the constant voltage; and a compensating unit, having a positive temperature coefficient and coupled in series to the resistor, for compensating a resistance variation of the resistor for a temperature variation.

Abstract: An integrated circuit that includes at least one tunneling device voltage reference circuit for use in low voltage applications is disclosed. The tunneling device voltage reference circuit includes a pair of voltage dividing device stacks, one having a linear voltage output and the other having a non-linear voltage output. A feedback circuit supplies a regulated voltage to each of the voltage dividing stacks so that the output voltages of the two device stacks equalize. Once the feedback circuit has locked, any one of the device stack output voltages and the regulated voltage may be used as a voltage reference.

Abstract: A device for adaptively controlling a voltage supplied to circuitry in substantially close proximity to the device, comprising a processing module, a first tracking element coupled to the processing module and producing a first value indicative of a first estimated speed associated with the circuitry, and a second tracking element coupled to the processing module and producing a second value indicative of a second estimated speed associated with the circuitry. The processing module compares each of the first and second values to a target value and causes a voltage output to be adjusted based on said comparison.

Abstract: A power managing apparatus is utilized to control a first supply voltage, a second supply voltage, and a substrate voltage of a digital circuit. The power managing apparatus includes a voltage generating device, for generating a first reference voltage and a second reference voltage; and a voltage switching device, coupled to the voltage generating device, for adjusting the first supply voltage, the second supply voltage, and the substrate voltage. When the digital circuit operates in a first operating mode, the voltage switching device outputs the second reference voltage to be the first supply voltage and the substrate voltage; and when the digital circuit operates in a second operating mode, the voltage switching device outputs the first reference voltage to be the first supply voltage, and outputs the second reference voltage to be the second supply voltage.

Abstract: Various systems and methods for device configuration are disclosed herein. For example, some embodiments of the present invention provide semiconductor devices that include a fuse blow circuit. The fuse blow circuit provides two fuse blow outputs. Assertion of one of the fuse blow outputs causes one electronic fuse to blow, and assertion of the other fuse blow output causes another electronic fuse to blow. One of the electronic fuses represents a configuration bit while the other electronic fuse represents an inversion status bit indicating an inversion to be applied to the configuration bit. Both the configuration bit and the inversion status bit are applied to an inverter which operates to invert the configuration bit based at least in part on the inversion status bit.

Abstract: A charge pump control circuit and a control method for controlling charge pumps are disclosed. The output terminal of the charge pump is coupled to a load circuit. The charge pump control circuit includes a detecting and controlling circuit and a controlled oscillator. The detecting and controlling circuit is used to detect the load status of the load circuit and output a control signal according to the load status. The controlled oscillator receives the control signal and outputs at least one clock signal. According to the control signal to control a frequency of the clock signal, the charge pump control circuit controls the charge pump.

Abstract: A dual mode voltage supply circuit (50) includes an active mode voltage supply circuit (58) and a passive mode voltage supply circuit (60). The active mode voltage supply circuit (58) is selectively operative to supply a voltage (57) based on mode control information (22). The active mode voltage supply circuit (58) is operative to provide a first current capacity. The passive mode voltage supply circuit (60) is operatively coupled to the active mode voltage supply circuit (58). The passive mode voltage supply circuit (60) is operative to supply the voltage (57) when the active mode voltage supply circuit (58) is not supplying the voltage (57). The passive mode voltage supply circuit (60) is operative to provide a second current capacity that is less than the first current capacity.

Abstract: A semiconductor integrated circuit is provided including a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The integrated circuit includes an interblock interface circuit provided on a signal path between an elected circuit block and a branch point at which the signal path branches into different branch paths so as to connect to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission from the elected circuit block to the other circuit blocks, and includes a storage unit for storing a signal right before the power cut-off.

Abstract: An internal voltage generating circuit detects a level of a back bias voltage or a pumping voltage and controls a period of an oscillating signal based on the result of counting timing when the detected voltage is lower than a reference voltage. The internal voltage generating circuit includes a back bias/pumping voltage detector for detecting a level difference between a back bias/pumping voltage and a reference voltage, a period controller for controlling a period of an oscillating signal based on the detection result of the back bias/pumping voltage detector, and a pumping unit for pumping the back bias/pumping voltage according to an activation period of the oscillating signal.

Abstract: A current mirror has an input bipolar device and an output bipolar device, a first MOSFET device to control a current in the input bipolar device, and a second MOSFET device to control a bias current to common base terminals of the input and output bipolar devices. An output stack may be coupled to the bipolar output device, and may include at least one output MOSFET device.