Abstract: An active LC band pass filter 10 includes a single LC pair and a plurality of active amplifiers providing a number of separate resonance circuits. The active amplifiers compensate ohmic losses, high frequency skin effects, and high frequency radiation. Each circuit has a resonance frequency that is adjustable by changing only the parameters of one or more active amplifiers. The filter 10 has a very high adjustable quality value Q, very low shape factor S, a relatively high signal-to-noise ratio, and a very large voltage gain that increases with frequency. High frequency performance is not affected by the quality of the LC pair, being limited only by the high frequency performance of the amplifier components. Also disclosed is a method for processing an electronic signal using the active LC band pass filter 10.

Abstract: A semiconductor integrated circuit device comprises: a circuit block, a first MOS transistor, a first power line, a second power line, a third power line, and a drive circuit. The first MOS transistor is connected between the first and second power lines. The circuit block is connected between the second and third power lines. The drive circuit controls a voltage supplied to a gate of the first MOS transistor. The first MOS transistor is off in a standby state and on in an operation state. During a shift from the standby state to the operation state and a shift from the operation state to the standby state, the drive circuit changes the voltage supplied to the gate of the first MOS transistor at a first rate, and then, changes the voltage supplied to the gate of the first MOS transistor at a second rate faster than the first rate.

Abstract: A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the coarse and fine delays. The system may use a single coarse delay line configured to generate two intermediate clocks from the input reference clock and having a fixed phase difference therebetween. The coarse delay line may have a hierarchical or a non-hierarchical structure. A phase mixer receives these two intermediate clocks and generates the final output clock having a phase between the phases of the intermediate clocks. The coarse shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs.

Abstract: A method for tuning a tunable filter includes inputting a control signal to the tunable filter and tuning the configuration of the tunable filter according to the control signal. When the control signal is at any one of a plurality of predetermined states, a step size of a characteristic frequency of the tunable filter is positively correlated with the characteristic frequency of the tunable filter.

Abstract: An electronic data storage system uses current comparison to generate a voltage bias. In at least one embodiment, a voltage bias generator, that includes a current differential amplifier, generates a current that charges a load to a predetermined voltage bias level. The current comparison results in the comparison between two currents, Iref and Isaref. The current Isaref can be generated using components that match components in the load and memory circuits in the system. In one embodiment, multiple sense amplifiers represent the load. By using matched components, as physical characteristics of the load and memory circuits change, the current Isaref also changes. Thus, the voltage bias changes to match the changing characteristics of the load and memory circuits. The voltage bias generator can include a current booster that decreases the initial charging time of a reactive load.

Abstract: System and method of calibrating delay mismatch for high-spectral purity applications. For example, a method includes measuring the delay of one delay element at a time in a fixed topology by moving a time reference generated by an auxiliary delay-locked loop. The auxiliary DLL may have a replica structure of the primary DLL being calibrated. The calibration method uses one output clock signal of the primary DLL and measures delay mismatch using a reference phase previously measured using the same topology. The calibration method takes into account all delay mismatches in the topology up to the primary DLL output clock signal, including any delay generated by an associated multiplexer.

Abstract: A circuit includes a plurality of stages each including a MOS transistor and a capacitor of which one end is connected to one of a drain and a source of the MOS transistor. The plurality of stages are connected with each other by cascade connection of the MOS transistors. A gate of the MOS transistor is connected electrically to one of the drain and the source thereof in each stage, and a substrate for at least one pair of adjacent MOS transistors are connected electrically to one of the drain and the source of one of the pair. The back bias effect is suppressed, and the layout area is reduced. Further, a plurality of booster capacitors connected in series are provided in succeeding stages, thereby suppressing degradation of breakdown voltage of each capacitor.

Abstract: A trimmer device for adjusting a reference signal of a target circuit is disclosed. The trimmer device includes: a switch controlling module and an impedance adjustment circuit. The switch controlling module includes: a fuse, selectively being melted according to the reference signal; and a control signal generating circuit, for generating a control signal according to the melting condition of the fuse. The impedance adjustment circuit includes: a switch module, being selectively conductive according to the control signal; and an impedance network, for determining an equivalent impedance of the impedance network according to the conducting condition of the switch module to further adjust the reference signal.

Abstract: A semiconductor integrated circuit apparatus and an electronic apparatus having a power control function configured from power control MOS transistors such that leakage current and on-resistance at the time of cut-off is sufficiently small in actual use. The semiconductor integrated circuit apparatus includes a CMOS logic circuit, a first pseudo power supply line connected to a high potential side power supply terminal of the CMOS logic circuit, a second pseudo power supply line connected to a low potential side power supply terminal of the CMOS logic circuit, and a power control NchMOS transistor connected across the second pseudo power supply line and a low potential side power supply line, with the substrate and gate of the power control NchMOS transistor being electrically connected. The gate and the substrate may also be connected via a current limiter utilizing a source follower of a depletion type NchMOS transistor.

Abstract: An apparatus and method for reducing EMI generated by a power conversion device, as well as a power conversion device employing such apparatus or method (and/or devices employing such a power conversion device) are disclosed. In at least some embodiments, the apparatus includes a hybrid filter for use in reducing EMI. The hybrid filter includes a passive filtering component, and an active filtering component coupled at least indirectly to the passive filtering component. The active filtering component includes a voltage controlled voltage source, and the hybrid filter operates to reduce a level of a common mode current, whereby the EMI generated due to the common mode current is reduced.

Abstract: A voltage controller (150), the controller comprising: a voltage comparator (700) operative to provide a digital error signal (152); a compensator (300) operative to determine a digital control signal (154) based on said provided error signal; and a modulator (400) operative to provide a power control signal (156) based on said determined digital control signal, wherein said comparator, said compensator, and said modulator are implemented entirely with digital logic gates.

Abstract: A noise reduction circuit outputs a signal corresponding to a voltage difference between two different signals. The noise reduction circuit includes: an amplifier circuit for amplifying the two different signals at different timings; and a voltage difference detection circuit for detecting a voltage difference between the two different signals amplified by the amplifier circuit. The noise reduction circuit accumulates, a predetermined number of times, an electric charge corresponding to the voltage difference detected by the voltage difference detection circuit and combines the accumulated electric charges to output a resultant electric charge.

Abstract: A supply voltage switching circuit for a computer includes a chipset, a first transistor and a second transistor. The chipset includes a first MOSFET and a second MOSFET. A 5V system voltage and a 5V standby voltage are respectively inputted to sources of the first MOSFET and the second MOSFET. Gates of the first MOSFET and the second MOSFET are respectively coupled to collectors of the first transistor and the second transistor. Emitters of the first transistor and the second transistor are coupled to a first terminal for receiving a control signal. A 1.8V standby voltage is separately inputted to bases of the first transistor and the second transistor. A 12V system voltage and the 5V standby voltage are respectively inputted to collectors of the first transistor and the second transistor. A second terminal is connected between the drain of the first MOSFET and the drain of the second MOSFET.

Abstract: A bandgap voltage reference circuit is provided that includes a PTAT source whose polarity reverses at a determinable temperature. The PTAT source is combined with a CTAT source in a manner to remove the effects of the slope of the CTAT source such that a voltage reference may be generated. A method of operating such a circuit is also described.

Abstract: An internal voltage generating circuit includes a first detector that compares an internal voltage and a first reference voltage to output a first detection signal. A second detector compares a supply voltage and a second reference voltage to output a second detection signal. A loop selection oscillator performs an oscillation operation in response to the first detection signal, selects a first loop or a second loop for performing the oscillation operation in response to the second detection signal, and outputs an oscillation signal. A charge pump performs a pumping operation according to the output of the loop selection oscillator and generates the internal voltage.

Abstract: A substrate voltage generating circuit including level shifting circuits, a first power supply node of a first potential level VDD a second power supply node of a second potential level VSS lower than the first potential level, and an output node OUT.vbb having a third potential level VBB lower than the second potential level. The level shifting circuits are coupled between the first power supply node and the output node, receiving an input signal having the first and second potential levels, and outputting an output signal VBB having the first potential level and the third potential level.

Abstract: A differential amplifier is disclosed. The differential amplifier includes a first load element coupled between a first voltage and a first node. A second load element is coupled between the first voltage and a second node. A current source is coupled between a second voltage and a third node. A first input element is coupled between the first node and the third node and receives an input signal so as to adjust a voltage level of the first node. A second input element is coupled between the second node and the third node and receives a reference voltage signal so as to adjust a voltage level of the second node. A third input element is coupled between the second node and the third node and receives the input signal so as to adjust the voltage level of the second node.

Abstract: An Op amp circuit is used to provide higher capacitance to a power network to remove unwanted high frequency components from the power signal. At the primary power line frequency, a lower capacitance is presented by the circuit.

Abstract: In a charge pump circuit, the slew rate at which a clock signal is fed to charge transfer transistors is changed according to the output voltage. This configuration helps alleviate rush currents at start-up without unduly lowering efficiency.

Abstract: This disclosure concerns a semiconductor integrated circuit that includes a semiconductor substrate, a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other, a plurality of MOS transistors formed in the well regions and a substrate bias generator that applies substrate biases to the individual well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.