Abstract: A method for determining power consumption in a data storage system is provided. The method comprises determining data access patterns for at least a first storage device in a storage system based on operations performed by the first storage device; and calculating power consumption for the storage system by interpolating costs associated with the operations performed by the first storage device, wherein the cost associated with each operation is determined based on: (1) various levels of activities for the first storage device and a mix of workload characteristics, and (2) predetermined power consumption measurements obtained from one or more benchmarks for same operations performed by a second storage device in a test environment.

Abstract: In one embodiment, the present invention includes a method for generating a list of files accessed during an operating system (OS) boot process to profile the OS boot process, and optimizing the list of files to generate an optimized file list for use in future OS boot processes, where the optimizing is according to a first optimization technique if the files were accessed from a solid state medium and according to a second optimization technique if the files were accessed from a rotating medium. Other embodiments are described and claimed.

Abstract: A computer has a plurality of sleeping modes to be switch directly. The power supply assemblies provide a plurality of power supplies to elements in the computer. The storage module is used to store executing data corresponding to each sleeping mode. The power management module is used to set the number of the power supply assemblies which need to be switched on in each sleeping mode. The control module determines the sleeping mode which is switched to according to a received trigger event and sends a first switching signal to the storage module to make the storage module store the executing data and a second switching signal to the power management module to make the power management module set the number of the power supply assemblies and switches the sleeping mode of the computer directly.

Abstract: In a Power over Ethernet (POE) system, a power source equipment (PSE) device configured to deliver power to one or more powered devices (PDs) over a plurality of Ethernet transmission lines. The PSE interface includes a multi-port transmission line connector capable connecting to multiple Ethernet transmission lines, and a power source equipment (PSE) controller module integrated with the multi-port transmission line connector. The PSE controller module is capable of semi-automatic mode and legacy detection of one or more of the PDs that are coupled to the Ethernet transmission lines. The PSE controller module includes a plurality of PSE controllers corresponding to the Ethernet transmission lines, including a master PSE controller and plurality of slave PSE controllers coupled to the master PSE controller. The master PSE controller controls the slave PSE controllers, so as to provide power management to said corresponding PD devices, without an external microcontroller.

Abstract: Includes receiving, from a link partner, a message specifying a link partner receive wake time and resolving to the lesser of the received link partner receive wake time and a local transmit wake time.

Abstract: A system and method are provided for booting a computing device using a NAND flash memory. Boot code stored in the NAND flash memory is transferred to a RAM for execution by the CPU. Operating system program stored in the NAND flash memory is transferred to a system memory for execution therefrom by the CPU after system boot.

Abstract: Methods, systems, apparatuses and program products are disclosed for providing power/energy control. HPM (Hierarchical Power Management) systems provide for and improve on the power management support beyond what is available in current PC notebooks and desktops.

Abstract: A host device capable of communicating with an external network. The host device may comprise a power-application unit and a network interface. The power-application unit may receive from a power-supply unit a first power-supply output having a first voltage level and a second power-supply output having a second voltage level. The power-application unit may be controllable for producing selectively a first power-application output having a third voltage level from the first power-supply output and a second power-application output having a fourth voltage level from the second power-supply output. The network interface may transmit data to and receive data from an external network, and may be powered at least in part by the first and second power-application outputs.

Abstract: An electronic device and method for secure embedded operating system update within embedded system. The embedded system includes a random-access memory, a non-volatile storage unit and a processing unit. The non-volatile storage unit defines a boot sector, a first sector and a second sector and contains a boot loader in the boot sector, an initialization variable in the boot sector and an embedded operating system in the first sector. The second sector is provided for storing another embedded operating system. The processing unit is coupled to the random-access memory and the non-volatile storage unit and is capable of executing the boot loader in order to copy one of the embedded operating systems from either the first sector or the second sector of the non-volatile storage unit into the random-access memory according to the current value of the initialization variable and then executing the loaded embedded operating system.

Abstract: Two clock domains of a data processing device are each synchronized with a different clock signal. The clock signals are generated by clock generation logic. The clock generation logic also generates a transfer enable signal based on the relative frequency of each clock signal to indicate when data can be transferred between the clock domains. Further, as the relative frequency of the clock signals change, the timing of the transfer enable signal also changes to ensure reliable data transfer.

Abstract: Disclosed are systems, methods, and computer program products for managing power states in processors of a data processing system. In one embodiment, the invention is directed to a data processing system having dynamically configurable power-performance states (“pstates”). The data processing system includes a processor configured to operate at multiple states of frequency and voltage. The data processing system also has a power manager module configured to monitor operation of the data processing system. The data processing system further includes a pstates table having a plurality of pstate definitions, wherein each pstate definition includes a voltage value, a frequency value, and at least one unique pointer that indicates a transition from a given pstate to a different pstate.

Abstract: A filter driver that is loaded during an initial part of the boot process enable operating systems that are not capable of booting from central storage to be booted from central storage. According to this technique, an initial set of operating system files is loaded into system memory from a local storage volume. The initial set of files includes a small subset of all of the operating system files and includes a boot loader, a kernel, boot time drivers, a file system driver, and a filter driver. The filter driver takes control over the loading of the remainder of the operating system files, so that these files are loaded from central storage instead of the local storage volume.

Abstract: An integrated circuit (100) may receive a boot loader code (114) via a debug access port (105), wherein a boot logic is operative to block, upon a reset (123) of the programmable processor (103) from the debug access port (105), commands and to the programmable processor from the debug access port, while still allowing the reset (123) command and while allowing write access to memory (112) to receive the boot loader code image (114) written to memory (112). The boot logic also blocks commands to the memory subsystem (109) from the debug access port and turns off write access to memory (112) after allowing the boot loader code image (114) to be written. The boot logic validates the boot loader code image (114) by performing a security check and jumps to the boot loader code image (114) if it is valid, thereby allowing it to run on the programmable processor (103). The boot logic may be logic circuits, software or a combination thereof.

Abstract: A method and apparatus for self-monitoring to identify an occurrence of a threshold and rebooting in response to the occurrence of the threshold is provided. In an embodiment, a data processing apparatus comprises one or more processors; logic coupled to the one or more processors and comprising one or more stored sequences of instructions which, when executed by one or more processors, cause the one or more processors to obtain a threshold associated with the apparatus; self-monitor the apparatus to identify an occurrence of the threshold; and self-reboot the apparatus responsive to the occurrence of the threshold.

Abstract: There is provided a signal synchronization method of performing signal synchronization between a device which operates in synchronization with a first clock signal and a processor which operates in synchronization with a second clock signal with a different cycle from that of the first signal.

Abstract: A computer-readable medium is disclosed. The computer-readable medium stores a virtualized service tool application program for running on a computer running an existing operating system platform. The virtualized service tool application program has operating system software configured to execute as an internal operating system platform separate from the existing operating system platform, and that is configured with settings that permit the computer to communicate with one or more machines coupled to the computer. The virtualized service tool application additionally has a service module configured to perform service-related tasks for the one or more machines coupled to the computer.

Abstract: A memory device is provided. The memory device includes a plurality of memory chips coupled in series, and a register serially coupled to the memory chips. The register includes an integrated delay-locked loop. The memory device may be included in a processing system. Moreover, a method for improving timing budgets in a registered dual in-line memory module (RDIMM) may be implemented using the memory device having a register with an integrated delay-locked loop.

Abstract: A blade computer system includes a plurality of client devices, a blade enclosure having a plurality of blades therein, and an allocation server configured to allocate and deallocate the blades to and from the client devices. The blade enclosure is configured to place individual ones of the blades into or out of a sleeping state responsive to network messages received from the allocation server.

Abstract: The circuit, typically a delay-locked loop, comprises a phase detector, a first counter, a second counter, and a comparator. The phase detector compares a phase of a first clock signal with a phase of a second clock signal. The first counter generates first count signals and adjusts the first count signals when the phase detector indicates that the phases of the first and the second clock signals are out of alignment. The second counter generates second count signals. The first comparator generates a first comparison signal in response to a comparison between the first count signals and the second count signals. The second clock signal is generated in response to the first comparison signal.

Abstract: Power consumption reduction of a mirrored RAID storage subsystems is disclosed, wherein data are mirrored to a secondary mirror disk system, the secondary mirror disk system alternates between an operational stage and a power-save stage, wherein data to be mirrored to the secondary mirror disk system is saved in a substantially always operational pre-stage storage if the secondary mirror disk system is in a power save stage and subsequently moved from the pre-stage storage to the secondary mirror disk system when the secondary mirror disk system is operational.