Abstract: A self programming slave device controller is described which comprises interface circuitry and control circuitry. The interface circuitry is responsive to one or more configuration parameters to communicate data between the slave device controller and a slave device in accordance with the one or more configuration parameters. The control circuitry is responsive to one or more operating parameter signals indicative of one or more operating parameters influencing current performance characteristics of the slave device to set the one or more configuration parameters so as to control an access operation for accessing the slave device to accommodate the current performance characteristics of the slave device. In this way, an access operation can be conducted efficiently and reliably having regard to the current performance characteristics of the slave device.

Abstract: A system has a central processing unit (CPU) operable to operate in a sleep or low power mode and in an active mode, a plurality of system components operable to operate in a sleep or low power mode and in an active mode, and a direct memory access (DMA) controller operating independently from the CPU and operable to operate in a sleep or low power mode and in an active mode, wherein the DMA controller is further operable to transfer data from and to a memory or peripheral device, wherein when the system is in a sleep or low power mode, only the DMA controller and any system component which is necessary to perform a DMA transaction are switched into active mode.

Abstract: An electronic device for selectively reproducing information. The electronic device includes a display, a power supply for supplying power, a switch, and a processor. The switch is connected to the display and the power supply. The processor is connected to the switch. When the processor identifies that the selected information is audio type, the processor turns off the switch to disconnect an electrical connection between the power supply and the display. A power saving method for reducing the energy consumption of the electronic device is also provided.

Abstract: When a setting input through a control portion falls within the first setup range, the settings in the first setup storage are rewritten with the setting in the second setup storage. Since the setting was revised, the revision history including the setup content and the data of the setting is stored in a revision history storage. Next, a determination process for the revised setting is carried out. Specifically, it is determined whether a usually expected input setting from the control portion falls within the second setup range. When it does not fall within the second setup range, the controller determines that the input setting is not a proper value, and reads out the setting before revision, stored in the third setup storage to rewrite the settings in the first setup storage with it.

Abstract: A system for reducing power consumption in an electronic device comprising at least one electronic chip comprises a plurality of local access network (LAN) ports, a transceiver coupled between the LAN ports and the electronic chip, a PLA device, and a central processing unit (CPU). The CPU is configured to power off the electronic chip in response to a period of inactivity on the LAN ports and power on the electronic chip in response to a signal from the PLA device.

Abstract: A power management control apparatus including a memory unit configured to store a program for disabling a previously determined Link power management state when a system enters a specific operating state and for enabling the disabled Link power management state when the system is resumed, a processor configured to access the memory unit and to execute the program, and a control unit connected to the processor and the memory unit and configured to manage Link power based on a result of executing the program.

Abstract: An information handling system includes a processor, a memory device coupled to the processor, and a dedicated system service repository (DSSR) coupled to the processor. The DSSR is configured to store a base image that includes a plurality of partitions and a first system configuration image, wherein the first system configuration image is stored in a first partition of the plurality of partitions, wherein the first system configuration image is configured to provide in-band and/or out-of-band managed access to the DSSR when executed; and by accessing the first system configuration image, the DSSR is populated with a second system configuration image, wherein the second system configuration image is stored in a second partition of the plurality of partitions.

Abstract: A disk drive is disclosed wherein boot data is transmitted from a first plurality of data sectors to a host during a first boot operation, and a log is maintained identifying a plurality of the transmitted data sectors. The log is used to write the boot data to a boot disk space comprising a second plurality of data sectors. During a second boot operation, the boot data is pre-fetched from the second plurality of data sectors of the boot disk space and stored in a cache.

Abstract: Power management architectures, methods and systems for programmable integrated circuit are disclosed. One embodiment of the present invention pertains to a power management software architecture which comprises power management modules each associated with a respective driver. Each driver is associated with a component of a programmable integrated circuit and displayable as a graphic image within an on-screen display of an integrated circuit design tool for programming the programmable integrated circuit. In addition, each power management module is operable to report power consumption data customized to its respective driver. The power management software architecture also comprises a power source module associated with a power source for the programmable integrated circuit for reporting power supply characteristics.

Abstract: Computer software that manages the amount of power provided to a processing unit for a specific process task, optimizing the processing speed of that specific task without overheating the processing unit. In the optimization method, the software initially counts the number of operations completed during an initial subtask duration for the current process task, then recounts the number of operations completed during a repeat subtask duration when the voltage to the processing unit was increased incrementally based on its die size. The software then determines whether to (a) repeat such steps until the operations count stops increasing (and save the completed-operations count of that subtask duration), or (b) whenever the temperature of the processing unit exceeds a failsafe temperature, save the completed-operations count of the immediately preceding subtask duration. The task may be processed continuously at that optimized performance level and power level.

Abstract: A power supply controlling apparatus includes: a first determination portion that determines whether a power supply is output from an information processing apparatus that outputs a video signal and is connected to the power supply controlling apparatus; a second determination portion that, when it is determined that the power supply is output from the information processing apparatus, determines whether a switch signal that indicates turning off a power supply of a power supply device supplying the power supply to the information processing apparatus has been received from a remote device outputting the switch signal in response to the depression of a switch, the power supply device and the remote device being connected to the power supply controlling apparatus; and a discard portion that discards the switch signal when it is determined that the switch signal has been received from the remote device.

Abstract: A method and an apparatus for preventing a basic input/output system (BIOS) from failing to enter a boot program are adapted to solve the problem that when a central processing unit (CPU) executes a first instruction after a computer is powered on, a start address to be executed is erroneously set as another corresponding start address, resulting in that a BIOS cannot enter a boot program. In the method of the present invention, a jump instruction is written to the corresponding start address, so as to enable an execution instruction to jump to a boot block of the BIOS when the start address is erroneously set in the computer, thus performing a normal boot operation.

Abstract: An apparatus for displaying a basic input output system (BIOS) power-on self-test (POST) code and a method thereof are provided. The apparatus includes a BIOS, a conversion module, and an output module. The BIOS is used for generating a POST code. The POST code is transmitted via a low pin count (LPC) interface. The conversion module receives the POST code and converts the POST code into a system management bus (SMBus) format. The output module is used for receiving and outputting the POST code transmitted by the conversion module. The output module is an SMBus interface.

Abstract: An integrated circuit includes an energy controller that generates a power supply voltage level for the integrated circuit based on a desired target frequency value for the integrated circuit. The energy controller configures a programmable hardware process sensor based on the power supply voltage level such that the programmable hardware process sensor is capable of mimicking the electrical characteristics of a predetermined critical path associated with the integrated circuit when operating at the power supply voltage level. By monitoring the frequency of the programmable hardware process sensor over a period of time, the energy controller can compare the monitored frequency to an expected value and determine whether the power supply voltage level can be adjusted or whether it should be maintained.

Abstract: Methods, apparatus, and products are disclosed for reducing power consumption while performing collective operations on a plurality of compute nodes that include: receiving, by each compute node, instructions to perform a type of collective operation; selecting, by each compute node from a plurality of collective operations for the collective operation type, a particular collective operation in dependence upon power consumption characteristics for each of the plurality of collective operations; and executing, by each compute node, the selected collective operation.

Abstract: In one embodiment a computer system comprises a processor and a memory module coupled to the processor and comprising logic instructions stored in a computer readable medium. The logic instructions, when executed, configure the processor to initiate power on self test processing in the basic input/output system of a computing device, compare a first identifier derived from a master boot record on the computing device with a second identifier stored in a memory location on the computing device, and implement a master boot record recovery process when the first identifier does not correspond with the second identifier.

Abstract: A control apparatus for accessing a memory card includes a bus, a detecting circuit, and an adjusting circuit. The bus is regarded as a signal transmission line between the control apparatus and the memory card. The bus has a power signal transmission line for providing the memory card with a power signal. The detecting circuit detects an operating status of the control apparatus and generates an indication signal when the operating status exceeds a predetermined operating range. The adjusting circuit is coupled to the bus and detecting circuit, and is utilized for adjusting a current passing through the power signal transmission line according to the indication signal without closing the power signal transmission line thereby making the operating status operated within the predetermined operating range.

Abstract: A computer system including at least one wake-up unit to sense whether a wake-up event occurs in a standby mode to decrease power consumption, a power supplying unit to supply power to the at least one wake-up unit, and a controlling unit to control a power supplying unit to the at least one wake-up unit in the standby mode according to predetermined setting corresponding to whether the at least one wake-up unit is operable.

Abstract: Techniques and apparatuses for providing power-aware thread scheduling and dynamic use of processors are disclosed. In some aspects, a multi-core system is monitored to determine core activity. The core activity may be compared to a power policy that balances a power savings plan with a performance plan. One or more of the cores may be parked in response to the comparison to reduce power consumption by the multi-core system. In additional aspects, the power-aware scheduling may be performed during a predetermined interval to dynamically park or unpark cores. Further aspects include adjusting the power state of unparked cores in response to the comparison of the core activity and power policy.

Abstract: An information processing unit is provided, which includes a first memory, a second memory, and a controller. The first memory stores a BIOS program beforehand that is executed at a startup of the unit so as to allow peripheral devices to operate normally. The first memory also stores initial BIOS data beforehand. The second memory stores BIOS data with which the BIOS program is executed. The controller is configured to: (a) if the initial BIOS data is updated, read the updated BIOS data including updated data from the first memory and writes the updated BIOS data into the second memory; and (b) execute the BIOS program using the updated BIOS data written in the second memory.