Abstract: A technique for dynamically controlling microprocessor power plane voltage levels includes storing in a memory on a voltage regulator voltage control identifiers in a table accessible according to performance state. In at least one embodiment of the invention, a method includes transitioning a voltage output of a voltage regulator to a next voltage level associated with a next performance state of a processor coupled to the voltage regulator based on a performance state indicator received from the processor and a corresponding entry of a performance state table. In at least one embodiment, the method includes loading performance state table entries into a storage device on the voltage regulator circuit.

Abstract: A method of controlling a portable electronic device includes receiving a power-down command, determining an automatic power-up date and time based on an earliest one of a next preset power-up and a next time-dependent event reminder, entering a power-down state, monitoring a date and time, and automatically powering up at the automatic power-up date and time.

Abstract: A system including an integrated circuit (IC) and a power supply regulator external to the IC. The IC operates in accordance with an active mode and a lower power mode, and is configured to retain a logical state during the low power mode. The power supply regulator is configured to i) supply a first voltage potential to a first pin of the IC during the active mode, and ii) disable the first voltage potential during the low power mode. The IC is configured to provide a first feedback signal from an internal supply of the IC to the power supply regulator via the first pin.

Abstract: A data processing apparatus is switchable between a power saving mode and a normal operating mode. A transition triggering event determining section determines an event (e.g., detection of a document or operation of a power saving key) that causes the data processing apparatus to shift from the power saving mode to the normal operating mode, and a transition triggering event holding section stores the event. Then, a mode switching section causes the data processing apparatus to shift from the power saving mode to the normal operating mode in accordance with the event. An execution priority determining section determines based on the event, an execution priority level and/or an order of precedence in which a plurality of programs are executed during the normal operating mode. A program controlling section executes the plurality of programs in accordance with the execution priority level and/or an order of precedence.

Abstract: A system and method for policing bad powered devices in power over Ethernet. Degradation of components within powered devices can lead to noise and ripple that exceed specified thresholds. This noise and ripple can adversely impact the operation of the power sourcing equipment. A noise detector implemented in the power sourcing equipment can detect the presence of such noise and ripple and modify the application of power to the particular port.

Abstract: A resume signal hold circuit holds an assertion of a resume signal instructed while the circuit block is in a stand-by mode. A resume signal mask circuit is provided between the circuit block and the resume signal hold circuit, and masks the signals while the circuit block is in the stand-by mode so that no signal can be input to the circuit block. A power saving control circuit causes the resume signal hold circuit to hold the assertion of the event signal and causes the resume signal mask circuit to mask the signals while the circuit block is in a stand-by mode. The power saving control circuit also causes the resume signal hold circuit to cancel the holding of the assertion of the resume signal after the completion of the resume setting of the circuit block and cancelling of the signal masking by the resume signal mask circuit.

Abstract: Embodiments of the present invention provide a method and apparatus for managing power states in a personal computing device, while maintaining a perception by the user of “instant on” functionality. In various embodiments of the invention, the power states are presented to the user as a simple on/off option and the power management protocol is not visible within the user interface of the personal computing device thereby providing the user with the impression that the system is operating with a simple binary on/off protocol.

Abstract: A method, chip and computer program product for booting from a secondary boot source. In one embodiment, the method includes: (1) retrieving primary boot code from an on-chip primary boot source on the same chip as a processor, the primary boot code comprising at least a boot discovery algorithm for determining the location of an external secondary boot source external to said chip, (2) executing the primary boot code on the processor, including the boot discovery algorithm, thus operating the processor to check each of a plurality of locations to determine the location of the external secondary boot source, (3) retrieving the secondary boot code from the determined location and (4) continuing the booting of the processor by executing the secondary boot code on the processor.

Abstract: A dynamic clock frequency module includes a request evaluation module configured to generate a sum of requests to utilize a system bus from a plurality of modules. A frequency assignment module is configured to calculate a clock frequency for the system bus in response to the requests and adjust the clock frequency between at least two non-zero frequency values. A pulse stretch module is configured to increase a period of time that at least one of the requests is asserted in response to the sum.

Abstract: Embodiments of the invention disclose a system and a method for estimating the power consumption of virtual servers that operate in various hardware configurations and making a charge. The system consists of a resource utilization measurement unit that measures utilization of a hardware resource by an operation of a virtual server. The system also includes a conversion unit that converts the utilization of the hardware resource measured by the resource utilization measurement unit to utilization of a hardware resource in a case where the operation of the virtual server is performed in a reference server including a preset hardware configuration.

Abstract: An apparatus and method for controlling power of a fixing unit is provided. The apparatus includes a power supply unit supplying DC power to the fixing unit, and a power controller controlling the power supply unit to gradually increase a DC power supply time until a pre-set time is reached. Accordingly, a flicker characteristic can be reduced by gradually increasing a supply time of DC power to the fixing unit.

Abstract: A multiple instruction execution modules device that comprises a first instruction execution module and a second instruction execution module and a context switch controller; wherein the first instruction execution module is logically identical to the second instruction execution module but substantially differs from the second instruction execution module by at least one power consumption characteristic; wherein the context switch controller controls a context switch between the first instruction execution module and the second instruction execution module; wherein an instruction execution module that its context has been transferred is shut down.

Abstract: A hardware wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism recognizes a programming idiom that indicates that a thread is waiting for an event. The wake-and-go mechanism updates a wake-and-go array with a target address associated with the event. The thread then goes to sleep until the event occurs. The wake-and-go array may be a content addressable memory (CAM). When a transaction appears on the symmetric multiprocessing (SMP) fabric that modifies the value at a target address in the CAM, the CAM returns a list of storage addresses at which the target address is stored. The wake-and-go mechanism associates these storage addresses with the threads waiting for an even at the target addresses, and may wake the one or more threads waiting for the event.

Abstract: A method for dynamically operating a multi-core processor system is provided. The method involves ascertaining currently active processor cores, identifying a currently active processor core having a lowest operating frequency, and adjusting at least one operational parameter according to voltage-frequency characteristics corresponding to the identified processor core to fulfill a predefined functional mode, e.g. power optimization mode, performance optimization mode and mixed mode.

Abstract: A portable electronic device is operative to facilitate power sharing with at least a second electronic device coupled thereto. The portable electronic device includes a battery power source, a first port adapted for connection to a first network connection and a second port adapted for connection to a second network connection. An input stage in the portable electronic device is connected to the first port. The input stage is operative to supply power received from the first network connection through the first port to the battery power source for recharging the battery power source. The portable electronic device further includes an output stage connected to the second port. The output stage is operative to supply power from the battery power source to the second network connection through the second port.

Abstract: Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.

Abstract: A dual BIOS program protecting method is provided for protecting a first BIOS program and a second BIOS program of a computer system. Firstly, a flag is switched from a first status to a second status during the refreshing of the first BIOS program. If the first BIOS program is successfully refreshed, the flag is switched from the second status to the first status. If the flag is in the second status when the computer system is booted, a first control signal is generated and the second BIOS program enters a write protection mode according to the first control signal.

Abstract: Various embodiments of the present invention provide systems and methods for governing power dissipation in a semiconductor device. For example, various embodiments of the present invention provide semiconductor devices that include a first function circuit, a second function circuit, and a power state change control circuit. The power state change control circuit is operable to determine a combination of power states of the first function circuit and the second function circuit that provides an overall power dissipation within a power dissipation level.

Abstract: Methods and systems for improved management of power allocation among a plurality of devices coupled to a controller. The controller and devices exchange messages to request, grant, and release allocations of power from a common power supply. In some embodiments, the controller may be a SAS/SATA controller and the messages exchanged may be SAS/SATA frames and/or primitives. In exemplary embodiments, the messages may request/grant a particular amount of power for each of one or more voltage levels provided by the power supply. In other exemplary embodiments, the messages may designate the duration of time during which the requesting device may utilize the allocated power. A power status message from the device to the controller may indicate a change in the power consumption by the device. Responsive to the power status message the controller may re-allocate power previously allocated to a device that has completed use thereof.

Abstract: According to one embodiment, a server apparatus includes a communication processor, a database and a controller. The communication processor starts up based on a startup program recorded in a processing memory, and performs a communication processing based on a service program recorded in the processing memory, after startup. The database stores the startup program in association with a first directory for specifying a first memory area, and stores the service program in association with a second directory for specifying a second memory area different from the first directory, The controller refers to the second directory stored in the database after the startup program starts, and reads the service program from the database based on the referred result, and further, records the read program in second memory area of the processing memory.