Patents Examined by Trung Dang
  • Patent number: 7718506
    Abstract: A method for forming isolation structure for MOS transistor is disclosed, which includes forming a first photoresist layer over a sacrificed oxide layer of a semiconductor substrate, patterning the first photoresist layer to define a PMOS active region and a PMOS isolation region; implanting nitrogen ions into the PMOS isolation region through the sacrificed oxide layer by using the first photoresist layer as a mask; removing the first photoresist layer; forming a second photoresist layer over the sacrificed oxide layer, patterning the second photoresist layer to define a NMOS active region and a NMOS isolation region; implanting oxygen ions into the NMOS isolation region through the sacrificed oxide layer by using the second photoresist layer as a mask; removing the second photoresist layer and the sacrificed oxide layer; and annealing the semiconductor substrate to form isolation structures of PMOS and NMOS, respectively.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: May 18, 2010
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Buxin Zhang, Yuan Wang
  • Patent number: 7718550
    Abstract: The present invention involves a method and apparatus for depositing a silicon oxide onto a substrate from solution at low temperatures in a manner that produces homogeneous growth of the silicon oxide. The method generally comprises the following steps: (a) Chemically treating a substrate to activate it for growth of the silicon oxide. (b) Immersing the treated substrate into a bath with a reactive solution. (c) Regenerating the reactive solution to allow for continued growth of the silicon oxide. In another embodiment of the present invention, the apparatus includes a first container holding a reactive solution, a substrate on which the silicon oxide is deposited, a second container holding silica, and a means for adding silica to the reactive solution.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: May 18, 2010
    Assignee: William Marsh Rice University
    Inventors: Andrew R. Barron, Elizabeth Anne Whitsitt
  • Patent number: 7718519
    Abstract: A method of producing a silicon carbide semiconductor device, including: step (A) of forming an impurity-doped region by implanting impurity ions 3 into at least a portion of a silicon carbide layer 2 formed on a first principal face of a silicon carbide substrate 1 having first and second principal faces; step (B) of forming capping layers 6 having thermal resistance on at least an upper face 2a of the silicon carbide layer 2 and on at least a second principal face 12a of the silicon carbide substrate 1; and step (C) of performing an activation annealing treatment by heating the silicon carbide layer 2 at a predetermined temperature.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: May 18, 2010
    Assignee: Panasonic Corporation
    Inventors: Kunimasa Takahashi, Chiaki Kudou
  • Patent number: 7714368
    Abstract: An imager pixel array capable of separating and detecting the spectral components of an incident light without the use of a color filter array. The imager pixel array employs a grating layer which allows one or more spectral components of incident light to be transmitted therethrough, but diffracts other spectral components of the incident light. Both the transmitted and diffracted spectral components can be sensed by photosensors in the imager pixel array and used in subsequent data processing, thereby improving the quantum efficiency of the imager device. The grating layer can be formed of first and second materials each having a refractive index which are substantially the same at a predetermined wavelength.
    Type: Grant
    Filed: June 26, 2006
    Date of Patent: May 11, 2010
    Assignee: Aptina Imaging Corporation
    Inventors: Zhaohui Yang, Ulrich C. Boettiger
  • Patent number: 7714393
    Abstract: Disclosed herein is a semiconductor device including an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor, the device having: a first insulating layer and a second insulating layer; and gate electrode contact plugs. Each of the gate electrodes of the N-channel insulated gate field effect transistor and the P-channel insulated gate field effect transistor is buried in a gate electrode formation opening provided in the first insulating layer.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: May 11, 2010
    Assignee: Sony Corporation
    Inventors: Kaori Tai, Masanori Tsukamoto, Masashi Nakata, Itaru Oshiyama
  • Patent number: 7714444
    Abstract: The present invention provides a conductive resin composition for connecting electrodes electrically, in which metal particles are dispersed in a flowing medium, wherein the flowing medium includes a first flowing medium that has relatively high wettability with the metal particles and a second flowing medium that has relatively low wettability with the metal particles, and the first flowing medium and the second flowing medium are dispersed in a state of being incompatible with each other. Thereby, a flip chip packaging method that can be applied to flip chip packaging of LSI and has high productivity and high reliability is provided.
    Type: Grant
    Filed: April 16, 2009
    Date of Patent: May 11, 2010
    Assignee: Panasonic Corporation
    Inventors: Seiichi Nakatani, Seiji Karashima, Takashi Kitae, Susumu Sawada
  • Patent number: 7709860
    Abstract: In a method of forming a semiconductor device on a semiconductor substrate (100), a photoresist layer (102) is deposited on the semiconductor substrate; a window (106) is formed in the photoresist layer (102) by electron beam lithography; a conformal layer (108) is deposited on the photoresist layer (102) and in the window (106); and substantially all of the conformal layer (108) is selectively removed from the photoresist layer (102) and a bottom portion of the window to form dielectric sidewalls (110) in the window (106).
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: May 4, 2010
    Assignee: Northrop Grumman Space & Mission Systems Corp.
    Inventors: Linh Dang, Wayne Yoshida, Xiaobing Mei, Jennifer Wang, Po-Hsin Liu, Jane Lee, Weidong Liu, Michael Barsky, Richard Lai
  • Patent number: 7700943
    Abstract: An embodiment of the present invention is a technique to functionalize carbon nanotubes in situ. A carbon nanotube (NT) array is grown or deposited on a substrate. The NT array is functionalized in situ with a polymer by partial thermal degradation of the polymer to form a NT structure. The functionalization of the NT structure is characterized. The functionalized NT structure is processed according to the characterized functionalization.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Nachiket R. Raravikar, James C. Matayabas, Jr.
  • Patent number: 7701039
    Abstract: At least one high aspect ratio via is formed in the backside of a semiconductor substrate. The at least one via is closed at one end by a conductive element forming a conductive structure of the semiconductor substrate. The backside of the semiconductor substrate is exposed to an electroplating solution containing a conductive material in solution with the active surface semiconductor substrate isolated therefrom. An electric potential is applied across the conductive element through the electroplating solution and a conductive contact pad in direct or indirect electrical communication with the conductive element at the closed end of the at least one via (or forming such conductive element) to cause conductive material to electrochemically deposit from the electroplating solution and fill the at least one via. Semiconductor devices and in-process semiconductor devices are also disclosed.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: April 20, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Warren M. Farnworth
  • Patent number: 7696561
    Abstract: A non-volatile memory device includes a first sensing line, a first word line, a depletion channel region, and impurity regions. The first sensing line and the first word line are formed adjacent to each other in parallel on a substrate. The first sensing line and the first word line have a tunnel oxide layer, a first conductive pattern, a dielectric layer pattern and a second conductive pattern sequentially stacked on the substrate. The depletion channel region is formed at an upper portion of the substrate under the first sensing line. The impurity regions are formed at upper portions of the substrate exposed by the first sensing line and the first word line.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: April 13, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Khe Yoo, Jeong-Uk Han, Hee-Seog Jeon, Sung-Gon Choi, Bo-Young Seo, Chang-Min Jeon, Ji-Do Ryu
  • Patent number: 7692309
    Abstract: An application-specific integrated circuit (ASIC) is customized using two non-adjacent via layers. An array of logic cells, each including a plurality of logic devices, are arranged in a plurality of non-customized base layers. A first routing grid, which includes a first non-customized metal routing layer, a customized via layer, and a second non-customized metal routing layer, is disposed on top of the plurality of non-customized layers. A second routing grid, which includes a third non-customized metal routing layer, another customized via layer, and a fourth non-customized metal routing layer, is disposed above the first routing grid. A non-customized via layer is disposed above the first routing grid and beneath the second routing grid. The routing grids and the non-customized via layer collectively facilitate routing connections to and from the logic cells.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: April 6, 2010
    Assignee: ViASIC, Inc.
    Inventor: William D. Cox
  • Patent number: 7687857
    Abstract: Integrated circuits and methods of forming field effect transistors are disclosed. In one aspect, an integrated circuit includes a semiconductor substrate comprising bulk semiconductive material. Electrically insulative material is received within the bulk semiconductive material. Semiconductor material is formed on the insulative material. A field effect transistor is included and comprises a gate, a channel region, and a pair of source/drain regions. In one implementation, one of the source/drain regions is formed in the semiconductor material, and the other of the source/drain regions is formed in the bulk semiconductive material. In one implementation, the electrically insulative material extends from beneath one of the source/drain regions to beneath only a portion of the channel region. Other aspects and implementations, including methodical aspects, are disclosed.
    Type: Grant
    Filed: December 14, 2007
    Date of Patent: March 30, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Gordon Haller
  • Patent number: 7687816
    Abstract: A light emitting diode and a method of producing white light from the light emitting diode with an active region producing an emission falling in a primary wavelength range. A first part of the active region covered with a first conversion element for converting the emission falling in the primary wavelength range to an emission falling in a second wavelength range. A remaining second part of the active region covered with a second conversion element for converting the emission falling in the primary wavelength rage to an emission falling in a third wavelength range. The light emitting diode is configured to control the intensity of the emission falling in the primary wavelength range to control the color point of the white light generated by mixing the emissions falling the second wavelength range and the third wavelength range.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: March 30, 2010
    Assignee: International Business Machines Corporation
    Inventor: Eric W B Dias
  • Patent number: 7683371
    Abstract: A display panel has a protection film having a recess. The recess is arranged above a storage electrode and corresponds to a location of the storage electrode in a plan view. A width of the recess is larger in plan view than a width of the storage electrode, and a pixel electrode is arranged on the protection film. The capacitance of a storage capacitor formed by charges stored in the pixel electrode and the storage electrode is determined by a thickness of the protection film and an overlapping area of the pixel electrode and the storage electrode.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: March 23, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chae-Woo Chung, Jeong-Ho Lee, Yong Woo Lee
  • Patent number: 7682892
    Abstract: An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source and drain doped with a first dopant type having a channel region of a second dopant type interposed between, and a gate electrode and a gate insulator over the channel region. A silicide layer forming a low resistance contact is at an interface region at a surface portion of the source and drain. At the interface region a chemical concentration of the first dopant is at least 5×1020 cm?3. Silicide interfaces according to the invention provide MOS transistor with a low silicide interface resistance, low pipe density, with an acceptably small impact on short channel behavior.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: March 23, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Borna Obradovic, Shashank Ekbote, Mark Visokay
  • Patent number: 7682931
    Abstract: When single crystal semiconductor layers are transposed from a single crystal semiconductor substrate (a bond wafer), the single crystal semiconductor substrate is etched selectively (this step is also referred to as groove processing), and a plurality of single crystal semiconductor layers, which are being divided in size of manufactured semiconductor elements, are transposed to a different substrate (a base substrate). Thus, a plurality of island-shaped single crystal semiconductor layers (SOI layers) can be formed over the base substrate. Further, etching is performed on the single crystal semiconductor layers formed over the base substrate, and the shapes of the SOI layers are controlled precisely by being processed and modified.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: March 23, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd
    Inventors: Shunpei Yamazaki, Ikuko Kawamata, Yasuyuki Arai
  • Patent number: 7683489
    Abstract: A semiconductor device and a fabricating method thereof are provided. A PMD layer and at least one IMD layer are formed on a semiconductor substrate. A through-electrode penetrates through the PMD layer and the IMD layer, and a connecting electrode connects to the through-electrode.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: March 23, 2010
    Assignee: Dongbu Hitek Co., Ltd.
    Inventors: Kyung Min Park, Jae Won Han
  • Patent number: 7679094
    Abstract: An oxynitride-based fluorescent material is formed of what results from substituting Eu for part of M of a general formula 2MO.Si3N4, wherein M denotes one or more elements selected from among Be, Mg, Ca, Sr and Ba. The oxynitride-based fluorescent material can be produced by a method comprising mixing an oxide of Be, Mg, Ca, Sr, Ba or Eu, or a compound of Be, Mg, Ca, Sr, Ba or Eu enabled by heating to form an oxide, and silicon nitride or a compound enabled by heating to form silicon nitride to obtain a mixture and firing the mixture in a vacuum or a non-oxidizing atmosphere at 1200 to 1900° C.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: March 16, 2010
    Assignee: Showa Denko K.K.
    Inventor: Kousuke Shioi
  • Patent number: 7679200
    Abstract: Various semiconductor chip crack stops and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor substrate that has a first corner defined by a first edge and a second edge. A crack stop is formed in the semiconductor substrate. The crack stop includes a first projection extending to the first edge and a second projection extending to the second edge to fence off a portion of the semiconductor substrate that includes the first corner.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: March 16, 2010
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Michael Z. Su, Jaime Bravo, Lei Fu, Jun Zhai
  • Patent number: 7675087
    Abstract: A surface mount light emitting device includes a substrate, a chip set, a wire set and an encapsulator. The substrate includes a base plate with four corners and four electrode layers arranged on the corners, each electrode layer has a top electrode extended to the top surface of the base plate, a bottom electrode extended to the bottom surface of the base plate and a trace extended toward the center of the top surface of the base plate. The chip set includes two resistor chips and two light emitting chips, the resistor chips arranged on two of the traces extended from two diagonal corners, the light emitting chips respectively arranged on the other two traces extended from the other two diagonal corners. The wire set includes two fuse wires electrically connected the resistor chips to the light emitting chips. The encapsulator is encapsulating the chip set and the wire set.
    Type: Grant
    Filed: December 1, 2008
    Date of Patent: March 9, 2010
    Inventors: Wen-Tsung Cheng, Wen-Ho Cheng