Patents Examined by Tuan Dinh
  • Patent number: 7220922
    Abstract: Component mounting equipment mounts an FPC board onto an LCD board. The LCD board has a first electrode section on one side edge and a second electrode section on another side edge. The FPC board has a first section on one side edge and a second section on another side edge. A first mounting apparatus mounts the first section on the first electrode section. A second mounting apparatus mounts the second section on the second electrode section. In the second component mounting apparatus, the second section is separated from the second electrode section at an ACF supply section and released at a pre-press bonding section.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: May 22, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenichi Nishino, Shinji Kanayama, Shinjiro Tsuji, Masayuki Ida, Tomotaka Nishimoto
  • Patent number: 7218529
    Abstract: A circuit arrangement includes a programmable memory element mounted on a circuit board, with programming contacts of the memory element connected to conductor paths of the circuit board. Data and/or programming codes stored in the memory element determine the functions of the circuit arrangement. To prevent unauthorized reprogramming of the memory element, at least one programming contact of the memory element and each conductor path connected thereto are covered or enclosed, so it is impossible to electrically contact this programming contact or the associated conductor paths without destroying the circuit arrangement. The circuit board is adhesively bonded to a board carrier, with the memory element and conductor paths sandwiched or encased therebetween. The circuit arrangement may be an engine controller for a motor vehicle, with security against unauthorized reprogramming for altering the performance of the engine.
    Type: Grant
    Filed: February 7, 2003
    Date of Patent: May 15, 2007
    Assignee: Conti Temic microelectronic GmbH
    Inventors: Gunther Breu, Hans-Joachim Diehm, Wolfgang Gutbrod, Friedhelm Heinke, Mathias Kuhn
  • Patent number: 7218892
    Abstract: A passive terminator between a plurality of nodes includes a first voltage divider configured to passively set a differential voltage level between a first voltage level and a second voltage level. The first voltage divider has a Thevenin resistance and is electrically connectable to a first node. At least a second voltage divider is configured to passively set the differential voltage level between the first voltage level and the second voltage level. The second voltage divider has the Thevenin resistance and is electrically connectable to at least a second node. A transformer is electrically connected between the first voltage divider and the at least second voltage divider. The transformer has a reactance that is substantially greater than the Thevenin resistance of the first voltage divider and the at least second voltage divider.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: May 15, 2007
    Assignee: The Boeing Company
    Inventor: Robert T. Beierle
  • Patent number: 7218530
    Abstract: Tails (20) projecting from an electrical component (12) that lies on a circuit board surface, are terminated to traces on a multi-layer circuit board (14) in a manner that minimizes the disadvantages of long through hole soldering and of surface mount techniques. A blind hole is drilled and plated to form a shallow well (70). The well is filled with a soldering composition (130). A tail (20) is projected downward into the soldering composition with the extreme tip of the tail lying above the bottom of the hole, and the soldering composition is heated to solder the tail to the hole plating.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: May 15, 2007
    Assignee: ITT Manufacturing Enterprises, Inc.
    Inventors: Scott Keith Mickievicz, John Edward Knaub
  • Patent number: 7217889
    Abstract: Two pairs of vias are arranged in a printed circuit board. A first pair of vias, which conveys a first signal pair, is arranged in a plane that is substantially equidistant from the vias in a second pair of vias, which conveys a second signal pair. Similarly, the second pair of vias is located in a plane that is substantially equidistant from each via in the first pair of vias. In some embodiments, such an arrangement reduces the crosstalk effect of the first signal pair on the second signal pair and vice versa.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: May 15, 2007
    Assignee: Cisco Technology, Inc.
    Inventors: Gopakumar Parameswaran, Cuong C. Ly, Douglas L. Yanagawa, Mark N. Yamashita, Yuval Bachar
  • Patent number: 7215540
    Abstract: A memory module includes a plurality of memory units, an assembling holder and an engaging arrangement. The assembling holder includes an elongated unit housing having at least an elongated receiving slot extended therealong. The engaging arrangement includes a first assembling joint provided at a side edge portion of one of the memory substrates, and a second assembling joint provided at a corresponding side edge portion of an adjacent memory substrate, wherein the first assembling joint is fittedly and detachably engaged with the second assembling joint of the adjacent memory unit to alignedly couple the memory units with each other in an edge to edge manner to inset into the receiving slot of the elongated unit housing.
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: May 8, 2007
    Assignee: Optimum Care International Tech. Inc.
    Inventor: Shih-Hsiung Lien
  • Patent number: 7215531
    Abstract: An apparatus is provided for packaging a laminated capacitor made to have a low ESL value and is used for a decoupling capacitor to be connected to a power supply circuit for a MPU chip providing a MPU. The laminated capacitor is accommodated within a cavity provided on a wiring board. The capacitor includes a plurality of first external terminal electrodes connected to first internal electrodes via a plurality of first feedthrough conductors and a plurality of second external terminal electrodes connected to second internal electrodes via a plurality of second feedthrough conductors. The first external terminal electrodes provided on a first major surface of a capacitor body are connected to via-hole conductors at the hot side for the power source within a substrate, and the second external terminal electrodes provided on first and second major surfaces are connected to grounding via-hole conductors and a mother board within the substrate.
    Type: Grant
    Filed: January 8, 2004
    Date of Patent: May 8, 2007
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasuyuki Naito, Masaaki Taniguchi, Yoichi Kuroda, Haruo Hori, Takanori Kondo
  • Patent number: 7215558
    Abstract: An integrated circuit packages comprises a printed circuit board, a non-metal connector, and a metal casing. The printed circuit board includes a ground ring around the non-metal connector. The metal casing substantially encloses the printed circuit board, and has an opening that allows access to the non-metal connector. The metal casing has a metal lip that makes physical and electrical contact with the ground ring of the printed circuit board. The metal casing may be used to help reduce EMI from a transmitter.
    Type: Grant
    Filed: January 5, 2005
    Date of Patent: May 8, 2007
    Assignee: Intel Corporation
    Inventors: Craig L. Schultz, Todd Micheal Petit, Joshua T. Oen
  • Patent number: 7212413
    Abstract: An electronic device with flexible printed circuit board structure. The electronic device includes a first flexible printed circuit board and a second flexible printed circuit board. The first flexible printed circuit board has a first bent portion. The second flexible printed circuit board has a second bent portion penetrating the first bent portion as the first and the second flexible printed circuit boards are bent simultaneously.
    Type: Grant
    Filed: May 12, 2004
    Date of Patent: May 1, 2007
    Assignee: AU Optronics Corp.
    Inventors: Che-Chih Chang, Chia-Jung Wu
  • Patent number: 7211736
    Abstract: In an implementation of connection pad layouts, a connection assembly includes a substrate assembly and connection pads disposed thereon. The connection pads form a configuration such that each connection pad is configured to align with a different terminal of an interconnect that is warped or otherwise has a non-linear alignment of terminals.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: May 1, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Noah Lassar, Mohammad Akhavain, Michael Martin
  • Patent number: 7211738
    Abstract: A bonding pad structure of a display device. A first conductive layer is formed overlying a substrate, a protection layer is formed overlying the substrate and the first conductive layer, and a second conductive layer is formed overlying the protection layer. An opening structure penetrates the second conductive layer and the protection layer to expose the first conductive layer. A third conductive layer is formed overlying the second conductive layer to contact the sidewall and bottom of the opening structure. Thus, the third conductive layer is electrically connected to the second conductive layer to provide a first electrical-connection path, and the third conductive layer is electrically connected to the first conductive layer to provide a second electrical-connection path.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: May 1, 2007
    Assignee: AU Optronics Corp.
    Inventors: Chun-Yu Lee, Shy-Ping Chou, Hui-Chang Chen
  • Patent number: 7209361
    Abstract: An electronic device includes a first module, which is protected against electromagnetic interference, and a second module. At least the first module has multilayer printed circuit boards with at least one inner layer with conductor tracks. The at least one inner layer forms flexible connections between the printed circuit boards of the first and second modules. The at least one inner layer forms a bushing capacitor together with other conductor tracks of the first module.
    Type: Grant
    Filed: August 9, 2004
    Date of Patent: April 24, 2007
    Assignee: Siemens Aktiengesellschaft
    Inventors: Reinhold Berberich, Dieter Busch, Reinfried Grimmel
  • Patent number: 7209347
    Abstract: A blade server system including a housing, a middle plane board, a server blade and a display panel is provided. The server blade is electrically connected to the middle plane board, while the display panel is electrically connected to the middle plane board and is slideably disposed on the housing for displaying the operation status of the server blade.
    Type: Grant
    Filed: April 14, 2005
    Date of Patent: April 24, 2007
    Assignee: Quanta Computer Inc.
    Inventors: Yuan-Chen Liang, Cheng-Wang Lin, Chun-Yi Lien, Chao-Jung Chen
  • Patent number: 7209363
    Abstract: A portable electronic device includes a removable panel (12), a latch assembly (20), and a base cover (30). The removable panel defines a first latch hole (1214). The base cover defines a third latch hole (344) corresponding to the first latch hole. The latch assembly includes a knob (21). The knob includes an operating portion (212), a shaft portion (214) extending downwardly from the operating portion, and a latching portion (216) extending from one end of the shaft portion. The latching portion is received through the first latch hole and the third latch hole. When the operating portion of the knob is pressed and rotated, the removable panel is secured to the base cover via the operating portion and the latching portion.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: April 24, 2007
    Assignees: Shenzhen Futaihong Precision Ind. Co., Ltd., Sutech Trading Limited
    Inventors: Ji Kun Liu, Qing Ming Huang, Chia-Hua Chen
  • Patent number: 7209365
    Abstract: A card retention device includes a latch member pivotally coupled on a side wall which is located in a chassis of a computer and is located corresponding to a distal end of an expansion card. The latch member includes a stem which has a first latch section and a second latch section on two ends. The first latch section is a stub to latch the upper edge of the distal end of the expansion card. The second latch section may be coupled with a third latch section formed on the side wall to enable the latch member to latch the expansion card and prevent the expansion card from becoming disengaging from the expansion slot where it is engaged.
    Type: Grant
    Filed: April 6, 2005
    Date of Patent: April 24, 2007
    Assignee: Inventec Corporation
    Inventor: Lin-Wei Chang
  • Patent number: 7209367
    Abstract: An electronic apparatus has a wiring board and connector units which are mounted at a case unit. The connector unit has an external connection surface connected with the external and a terminal installation surface, which is substantially flat and positioned at an opposite side to the external connection surface. A terminal of the connector unit is electrically connected with a pad positioned at a first surface of the wiring board via a connection member. The wiring board and the connector unit which are integrated are mounted at the case unit, with the first surface and the terminal installation surface facing the case unit. The case unit has an installation surface at which a recess for accommodating therein the connection member is arranged.
    Type: Grant
    Filed: April 13, 2006
    Date of Patent: April 24, 2007
    Assignee: Denso Corporation
    Inventors: Tetsuo Nakano, Yukihiro Maeda
  • Patent number: 7209364
    Abstract: A method according to one embodiment may include providing a circuit board assembly comprising a circuit board and a rotatable knob and at least one latch coupled to the knob via a linkage. The method of this embodiment may also include moving the at least one latch to a retracted position by rotating the knob, and inserting the circuit board assembly into a chassis. The method may then include moving the latch to an extended position. Of course, many alternatives, variations, and modification are possible without departing from this embodiment.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: April 24, 2007
    Assignee: Intel Corporation
    Inventors: James C. Shipley, Javier Leija, Christopher A. Gonzales, Christopher D. Lucero
  • Patent number: 7209362
    Abstract: A multilayer ceramic substrate with a cavity includes a multilayer composite member including a plurality of ceramic layers disposed one on another. A cavity is formed in the multilayer composite member such that an opening of the cavity is located in one principal surface of the multilayer composite member. A bottom-surface conductive film is disposed on the bottom surface of the cavity. A capacitor conductive film is disposed in the multilayer composite member such that the capacitor conductive film faces the bottom-surface conductive film via one of the ceramic layers, thereby forming a capacitor.
    Type: Grant
    Filed: July 7, 2003
    Date of Patent: April 24, 2007
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Tomoya Bando
  • Patent number: 7209366
    Abstract: An integrated circuit (IC) package includes a chip carrier and a chip mounted to the chip carrier. The chip carrier has a centrally located power delivery region and a peripherally located input-output (I/O) delivery region disposed in partially surrounding relationship to the power delivery region. Power and ground paths are disposed in the power delivery region and I/O signal paths are disposed in the I/O delivery region.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: April 24, 2007
    Assignee: Intel Corporation
    Inventors: Victor Prokofiev, Cengiz A. Palanduz
  • Patent number: 7203075
    Abstract: A film carrier tape for mounting electronic parts comprises an insulating film, a wiring pattern formed on a surface of the insulating film, and a solder resist layer formed by moving a squeegee using a screen mask of a prescribed pattern that is formed in such a manner that connecting terminal portions of the wiring pattern should be exposed. The edge of the solder resist layer is formed almost in parallel or almost at right angles to the moving direction of the squeegee used in the application of the solder resist. The solder resist layer can be formed by the use of a screen mask for solder resist coating in which the edge of the screen that is unmasked to apply the solder resist is formed almost in parallel or almost at right angles to the moving direction of the squeegee used in the application of the solder resist. According to the present invention, the fraction defective of the solder resist coating can be decreased.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: April 10, 2007
    Assignee: Mitsui Mining & Smelting Co., Ltd.
    Inventors: Akihiro Terada, Keisuke Yamashita