Abstract: A microelectromechanical device package and a low-stress inducing method for packaging a microelectromechanical device are disclosed in this invention. The microelectromechanical device is accommodated within a cavity comprised by a first package substrate and a second substrate, wherein a third substrate is disposed between and bonded to both the microelectromechanical device lower semiconductor substrate and the package bottom substrate. The first and second package substrates are then bonded so as to package the microelectromechanical device inside.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.

Abstract: A light emitting diode has a substrate having a heat radiation conductive member therein, and a light emitting element mounted on the substrate. At least a part of the light emitting element is directly brought into contact and electrically connected with the heat radiation conductive member.

Abstract: A light emitting diode and a method of the same are provided. The light emitting diode includes a light-emitting structure, a silicon substrate and a bonding layer. The light-emitting structure includes two semiconductor layers of different doped types. The light-emitting structure is capable of emitting light when a current passes through. The silicon substrate includes two zones of different doped types. The bonding layer is interposed between the light-emitting structure and the silicon substrate so that the semiconductor layer and the zone closest to the bonding layer are of different doped types.

Abstract: The invention provides an advanced metallization technique for fabricating a memory cell array on a substrate. The array is fabricated by forming discrete and self-aligned vias in a first layer disposed over the array to form contacts to each of the source and drain junction in the array. Further, self-aligned local area slotted vias are formed in a second layer that is disposed over the first layer to form local area interconnects that electrically shunt all of the source contacts/junctions. Further, discrete self-aligned drain extensions are formed over each of the formed drain contacts to electrically connect the junctions, and source contacts to the extensions. The formed vias, extensions, and slotted local area vias are simultaneously plugged and filled with a conductive material to form the memory cell array.

Abstract: A semiconductor device having a structure miniaturizable through simple fabrication steps and a method of fabricating a semiconductor device capable of remarkably improving production efficiency are obtained. The semiconductor device comprises a semiconductor chip including a semiconductor circuit having a prescribed function and an electrode on one main surface, a wire having a first end connected with the electrode and a second end having a connecting terminal connected to an external device and an insulator sealing at least the main surface of the semiconductor chip. The connecting terminal provided on the second end of the wire is a part formed while keeping a state integrated with the remaining part of the wire, and exposed on a bottom surface opposite to the upper surface of the insulator closer to the main surface.

Abstract: An active matrix substrate includes a load circuit including a first active element performing a switching operation of a load, the first active element including a semiconductor film of a substantially polycrystalline state; a drive circuit including a second active element controlling driving the load, the second active element including a semiconductor film of a substantially single crystalline state, a hole being provided to one of a part and a peripheral part of the semiconductor film, the hole functioning a starting point for crystallizing the semiconductor film; and a substrate on a same plane of which the load circuit and the drive circuit are formed.

Abstract: A semiconductor device includes a semiconductor substrate, cavities, and an element isolating region. The cavities, which are each shaped like a flat plate, are made in the semiconductor substrate. The element isolating region is formed in the surface of the semiconductor substrate and located at the sides of the cavities.

Abstract: A SiC material composition is selected to establish the barrier energy between the SIC gate and a gate insulator. Various embodiments of selected SiC material composition include a memory application, such as a flash EEPROM, and a light detector or imaging application.

Abstract: A packaging structure for optoelectronic components is formed by a first body, of semiconductor material, and a second body, of semiconductor material, fixed to a first face of said first body. A through window is formed in the second body and exposes a portion of the first face of the first body, whereon at least one optoelectronic component is fixed. Through connection regions extend through the first body and are in electrical contact with the optoelectronic component. The through connection regions are insulated from the rest of the first body via through insulation regions. Contact regions are arranged on the bottom face of the first body and are connected to said optoelectronic component via the through connection regions.

Abstract: An electrostatic discharge protection network that uses triple well semiconductor devices either singularly or in a series configuration. The semiconductor devices are preferably in diode junction type configuration.

Abstract: Off-chip driver (OCD) NMOS transistors with ESD protection are formed by interposing an P-ESD implant between the N+ drain regions of OCD NMOS transistors and the N-well such that the P-ESD surrounds a section of the N-well. The P-ESD implant is dosed less than the N+ source/drain implants but higher than the N-well dose. In another embodiment, N-well doping is used along with P-ESD doping, where the P-ESD doping is chosen such that it counterdopes the N-well underneath the N+ drains. The N-well, however, still maintains electrical connection to the N+ drains. This procedure creates a larger surface under the area where the junction breakdown occurs and an increased radius of curvature of the junction. The P-ESD implant is covered by N-type on three sides creating better parasitic bipolar transistor characteristics.

Abstract: An electrical component includes a base having at least a first ceramic section and a second ceramic section. The first ceramic section and the second ceramic section include different materials, which have resistances with negative temperature coefficients. The component also includes first and second contact layers on the base. The first and second ceramic sections are between the first and second contact layers. A plurality of stacks of electrically conductive electrode layers are arranged inside the base. Stacks of electrode layers are electrically connected to the first and second contact layers.

Abstract: In a vertical-type metal insulator field effect transistor device having a first conductivity type drain region layer, a plurality of second conductivity type base regions are produced and arranged in the first conductivity type drain region layer, and a first conductivity type source region is produced in each of the second conductivity type base regions. Both a gate insulating layer and a gate electrode layer are formed on the first conductivity type drain region layer such that a plurality of unit transistor cells are produced in conjunction with the second conductivity type base regions and the first conductivity type source regions, and each of the unit transistor cells includes respective span portions of the gate insulating layer and the gate electrode layer, which bridge a space between the first conductivity type source regions formed in two adjacent second conductivity base regions.

Abstract: An electro-optical device includes a pair of substrates including a first substrate and a second substrate, an electro-optical material sandwiched between the pair of substrates, a shading film having a predetermined pattern which is at least partially embedded in the first substrate at the surface facing the electro-optical material, display electrodes which are placed on the second substrate at the surface facing the electro-optical material, and lines connected to the display electrodes directly or through switching elements. In accordance with the electro-optical device having such a shading film, it is possible to reduce or prevent coating defects in an alignment layer, nonuniform rubbing treatment to the alignment layer, and cracking of a counter electrode due to the steps in the upper layers resulting from the formation of the shading film.

Abstract: A semiconductor device includes a semiconductor substrate in which an integrated circuit is formed and which includes interconnects and electrodes, the interconnects electrically connected with the semiconductor substrate, and the electrodes being formed on the interconnects; a resin layer formed on the semiconductor substrate; redistribution interconnects electrically connected with the electrodes; a plurality of external terminals which are formed on the redistribution interconnects and supported by the resin layer; and a plurality of dummy terminals supported by the resin layer without being electrically connected with the electrodes.

Abstract: Electrical devices comprised of nanoscopic wires are described, along with methods of their manufacture and use. The nanoscopic wires can be nanotubes, preferably single-walled carbon nanotubes. They can be arranged in crossbar arrays using chemically patterned surfaces for direction, via chemical vapor deposition. Chemical vapor deposition also can be used to form nanotubes in arrays in the presence of directing electric fields, optionally in combination with self-assembled monolayer patterns. Bistable devices are described.

Abstract: A composite film comprised of three layers is formed by ALD on a substrate with a substrate interface surface. A first layer is coupled to the substrate interface surface. The first layer provides adhesion to the substrate interface surface and initiation of layer by layer ALD growth. A second layer is positioned between the first and third layers and provides a conducting diffusion barrier between the substrate and subsequent overlaying film. A third layer has a surface that is configured to provide adhesion and a texture template in preparation for a subsequent overlaying film. The composite engineered barrier structures are applied to interconnect, capacitor and transistor applications.

Abstract: A light emitting diode (LED) and a method of making the same are disclosed. The present invention uses a metal layer of high conductivity and high reflectivity to prevent the substrate from absorbing the light emitted. This invention also uses the bonding technology of dielectric material thin film to replace the substrate of epitaxial growth with high thermal conductivity substrate to enhance the heat dissipation of the chip, thereby increasing the performance stability of the LED, and making the LED applicable under higher current.

Abstract: An MIM capacitor comprises first and second conductor patterns embedded in a first interlayer insulation film so as to extend continuously in a mutually opposing relationship and forming a part of a comb-shaped capacitor pattern, and third and fourth conductor patterns formed in a second interlayer insulation film separated from the first interlayer insulation film by a via-insulation film, such that the third and fourth conductor patterns extend in the second layer interlayer insulation film continuously in a mutually opposing relationship as a part of the comb-shaped capacitor pattern, wherein there is formed a fifth conductor pattern extending in the via-insulation film continuously in correspondence to the first and third conductor patterns so as to connect the first and third conductor patterns continuously, and wherein there is formed a sixth conductor pattern extending in the via-insulation film continuously in correspondence to the second and fourth conductor patterns so as to connect the second and f