Abstract: A method of forming a packaged semiconductor device includes attaching a backside surface of a semiconductor die to a major surface of a package substrate. A first conductive connector is formed over a portion of an active surface of the semiconductor die and a portion of the major surface of the package substrate. A first conductive connection between a first bond pad of the semiconductor die and a first substrate pad of the package substrate is formed by way of the first conductive connector. A bond wire connects a second bond pad of the semiconductor die to a second substrate pad of the package substrate. The first bond pad located between the second bond pad and an edge of the semiconductor die.

Abstract: A method of manufacturing a semiconductor device includes: forming a first stack structure; forming first holes penetrating the first stack structure; forming a second stack structure on the first stack structure; forming second holes penetrating the second stack structure; measuring first direction distances between edges of the first holes and edges of the second holes; and correcting a first direction position at which the second holes are to be formed. The second holes may include one of a first shift hole shifted in a positive first direction from a first hole and a second shift hole shifted in a negative first direction from a first hole.

Abstract: A multi-chip device is provided. The multi-chip device includes a first chip, a second chip mounted on the first chip, and a hardened printed or sprayed electrically conductive material forming a sintered electrically conductive interface between the first chip and the second chip.

Abstract: The present disclosure provides a chip package structure having a heat sink and a method making the same. The method includes: bonding a chip to a top surface of a package substrate and forming a heat-conducting lead having an arc-shape and placed on the chip in a vertical direction, a first end of the heat-conducting lead is connected with a surface of the chip, and a second end is connected with a solder ball; forming a plastic package material layer that protects the chip and the heat-conducting lead; forming a heat-conducting adhesive layer on the surface of the plastic package material layer, where the heat-conducting adhesive layer is connected with the solder ball on the second end of the heat-conducting lead; and forming a heat dissipation layer on a surface of the heat-conducting adhesive layer. With the present disclosure, the heat dissipation efficiency of the chip is effectively improved.

Abstract: A semiconductor device according to the present embodiment includes a wiring substrate. A semiconductor chip includes a semiconductor substrate having a first face and a second face on the opposite side to the first face, and an SRAM on the side of the first face, and is stuck to the wiring substrate on the side of the second face. The semiconductor chip includes a first metallic layer provided in the semiconductor substrate between the SRAM and the wiring substrate.

Abstract: A semiconductor package according to an aspect of the present disclosure includes a package substrate and a plurality of semiconductor chips stacked on the package substrate. Each of the semiconductor chips includes a chip body, at least one first side power pad and at least one first side ground pad that are disposed on a first side portion on one surface of the chip body, and at least one second side power pad and at least one second side ground pad that are disposed on a second side portion opposite to the first side portion on one surface of the chip body. One of the second side power pads is disposed point-symmetrically to corresponding one of the first side power pads with respect to a reference point on the one surface, and one of the second side ground pads is disposed point-symmetrically to corresponding one of the first side ground pads with respect to a reference point on the one surface.

Abstract: A step-type stacked chip packaging structure based on a resin spacer that includes: a plastic packaging material, a circuit board, a resin spacer, a first chip, a second chip and an electrical connection assembly. The resin spacer, the first chip, and the second chip are stacked on the circuit board respectively. The second chip is stacked on the first chip in a stepped manner. The circuit board, the first chip and the second chip are electrically connected together through the electrical connection assembly. The resin spacer uses a fiber glass fabric as its base material, a weight percent of the fiber glass fabric is 10-60 wt %, and the following components are attached to the fiber glass fabric as a percentage by the total weight of the resin spacer: 8-40 wt % of epoxy resin, 10-30 wt % of quartz powder, 2-10 wt % of aluminum oxide, 1-8 wt % of calcium oxide, and 1-8 wt % of curing agent.

Abstract: A semiconductor package includes a sub semiconductor package disposed over a substrate. The sub semiconductor package includes a sub semiconductor chip with chip pads on its upper surface, a sub molding layer that surrounds the sub semiconductor chip, and a redistribution conductive layer that is connected to each of the chip pads and extends over an upper surface of the sub molding layer. The redistribution conductive layer includes a signal redistribution conductive layer that extends onto an edge of the sub molding layer and has a signal redistribution pad on its end portion and a power redistribution conductive layer with a length that is shorter than a length of the signal redistribution conductive layer. The semiconductor package also includes a sub signal interconnector, sub power interconnector, and at least one main semiconductor chip formed over the sub semiconductor package and electrically connected to the substrate or the sub semiconductor chip.

Abstract: A lead frame includes a die paddle and a plurality of leads. The leads surround the die paddle. Each of the leads includes an inner lead portion and an outer lead portion connecting to the inner lead portion. The inner lead portion is adjacent to and spaced apart from the die paddle. A bottom surface of the inner lead portion is higher than a bottom surface of the outer lead portion. The bottom surface of the inner lead portion includes one or more supporting members disposed thereon. The one or more supporting members have a convex surface facing away from the inner lead portion.

Abstract: A method of forming a packaged semiconductor device includes attaching a backside surface of a semiconductor die to a major surface of a package substrate. A first conductive connector is formed over a portion of an active surface of the semiconductor die and a portion of the major surface of the package substrate. A first conductive connection between a first bond pad of the semiconductor die and a first substrate pad of the package substrate is formed by way of the first conductive connector. A bond wire connects a second bond pad of the semiconductor die to a second substrate pad of the package substrate. The first bond pad located between the second bond pad and an edge of the semiconductor die.

Abstract: A method including stacking a number of silicon dice such that one or more edges of the dice are in vertical alignment, where the one or more edges include a number of connection pads. The method also includes positioning a connecting wire on a substantially perpendicular axis to the one or more edges. The connecting wire includes a number of solder blocks formed thereon. The solder blocks are spaced at intervals associated with a distance between a first set of aligned connection pads on the dice. The connecting wire is positioned such that the solder blocks are in contact with the first set of aligned connection pads. The method also includes applying heat to cause the solder blocks to reflow and physically and electrically couple the connecting wire to the connection pads.

Abstract: A memory device includes a peripheral circuit region comprising a first substrate, a plurality of metal layers over the first substrate, and a first metal pad, a cell region comprising a second substrate, a plurality of gate lines over the second substrate, a plurality of upper interconnection layers in the second substrate, and a second metal pad, wherein the cell region is vertically connected to the peripheral circuit region by the first metal pad and the second metal pad, a common source line between the second substrate and the plurality of gate lines, the common source line comprising a through hole, and a word line cut region extending across the plurality of gate lines and extending through the through hole of the common source line to be connected to a first upper interconnection layer from among the plurality of upper interconnection layers.

Abstract: A display screen, a manufacturing method thereof, and an electronic device are provided. The display screen includes a cathode disposed on an organic light-emitting layer and a pixel definition layer and multiplexed as a first touch control electrode; a second touch control electrode disposed on the cathode; and a plurality of black matrices disposed on the second touch control electrode. Positions of the black matrices correspond to positions of second touch control units.

Abstract: A semiconductor package is provided. The semiconductor package may include a substrate, a chip stack disposed on the substrate, the chip stack including a plurality of semiconductor chips, a plurality of bonding wires electrically connecting the substrate to the plurality of semiconductor chips, a reinforcement layer disposed on the chip stack, and a molding layer surrounding side surfaces of the chip stack and the bonding wires and contacting side surfaces of the reinforcement layer. The reinforcement layer may include a lower layer including an adhesive, an intermediate layer disposed on the lower layer, and an upper layer disposed on the intermediate layer. The intermediate layer may have elongation in a range of 5% to 70%. The upper layer may have elongation less than 5%.

Abstract: A wire bonding apparatus includes: a first tensioner which forms, nearer a wire supply side than a bonding tool, a first gas flow for applying a tension toward the wire supply side on a wire; a second tensioner which forms, between the first tensioner and a pressing part of the bonding tool, a second gas flow for applying a tension toward the wire supply side on the wire; and a control part which controls the first tensioner and the second tensioner. The control part implements control, in a predetermined period after a first bonding step for bonding the wire to a first bonding point, to turn off at least the second gas flow of the second tensioner among the first tensioner and the second tensioner or to make at least the second gas flow smaller than in the first bonding step.

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Abstract: An organic light emitting diode display device and a method of fabricating same are provided. The organic light emitting diode display includes an electron transport layer disposed on a light emitting layer, and material of the electron transport layer comprises a soluble organic electron transport material. The electron transport layer can be formed by ink and by inkjet printing.

Abstract: A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.

Abstract: A semiconductor package includes a semiconductor die including a semiconductor substrate, a strain-sensitive component located within or over a metallization layer of the semiconductor die, wherein a parameter of the strain-sensitive component exhibits a longitudinal shift due to a longitudinal strain and a transverse shift due to a transverse strain, and a mold compound covering the semiconductor die and the strain-sensitive component. The semiconductor package, including the semiconductor die and the mold compound, defines an orthogonal package-induced strain ratio on the strain-sensitive component on the semiconductor die surface. The strain-sensitive component is located such that the longitudinal shift due to package-induced strains offsets the transverse shift due to the package-induced strains.

Abstract: An embodiment includes a first package component including a first integrated circuit die and a first encapsulant at least partially surrounding the first integrated circuit die. The device also includes a redistribution structure on the first encapsulant and coupled to the first integrated circuit die. The device also includes a first thermal module coupled to the first integrated circuit die. The device also includes a second package component bonded to the first package component, the second package component including a power module attached to the first package component, the power module including active devices. The device also includes a second thermal module coupled to the power module. The device also includes a mechanical brace extending from a top surface of the second thermal module to a bottom surface of the first thermal module, the mechanical brace physically contacting the first thermal module and the second thermal module.