Abstract: An integrated circuit (IC) device includes a peripheral circuit structure, a memory stack including a plurality of gate lines overlapping the peripheral circuit structure in a vertical direction on the peripheral circuit structure, an upper substrate between the peripheral circuit structure and the memory stack, the upper substrate including a through hole positioned below a memory cell region of the memory stack, a word line cut region extending lengthwise in a first lateral direction across the memory stack and the through hole, and a common source line located in the word line cut region, the common source line including a first portion extending lengthwise in the first lateral direction on the upper substrate and a second portion integrally connected to the first portion, the second portion penetrating the upper substrate through the through hole from an upper portion of the upper substrate and extending into the peripheral circuit structure.

Abstract: A method of determining a bonding status between wire and at least one bonding location of a semiconductor device is provided. The method includes the steps of: (a) bonding a portion of wire to at least one bonding location of a semiconductor device using a bonding tool of a wire bonding machine; and (b) detecting whether another portion of wire engaged with the bonding tool, and separate from the portion of wire, contacts the portion of wire in a predetermined height range, thereby determining if the portion of wire is bonded to the at least one bonding location.

Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode over the first and second high-k gate dielectrics. A portion of the gate electrode between the first nanostructure and the second nanostructure comprises: a first p-type work function metal; a barrier material over the first p-type work function metal; and a second p-type work function metal over the barrier material, the barrier material physically separating the first p-type work function metal from the second p-type work function metal.

Abstract: A display device is disclosed. The display device includes a substrate having a plurality of pixels, wherein each of the plurality of pixels includes at least one light emitting chip, and a structure on one side of at least one of the plurality of pixels. A base material of the light emitting chip is the same as a base material of the structure.

Abstract: An integrated circuit (IC) package includes a substrate having a first region and a second region. The substrate includes a conductive path between the first region and the second region. The IC package also includes a lead frame having a first member and a second member that are spaced apart. The IC package further includes a half-bridge power module. The half-bridge power module includes a capacitor having a first node coupled to the first member of the lead frame and a second node coupled to the second member of the lead frame. The half-bridge power module also includes a high side die having a high side field effect transistor (FET) embedded therein and a low side die having a low side FET embedded therein. A source of the high side FET is coupled to a drain of the low side FET through the conductive path of the substrate.

Abstract: An optoelectronic device includes an emitter of light rays and a receiver of light rays. The emitter is encapsulated in a transparent block. An opaque conductive layer is applied to a top surface and a side surface of the transparent block. The receiver is mounted to the opaque conductive layer at the top surface. An electrical connection is made between the receiver and the opaque conductive layer. A conductive strip is also mounted to the side surface of the transparent block and isolated from the opaque conductive layer. A further electrical connection is made between the receiver and the conductive strip.

Abstract: An organic light emitting diode (OLED) dual screen display is provided, including a first OLED display panel and a second OLED display panel opposite to the first OLED display panel. Both edges of the first OLED display panel and both edges of the second OLED display panel are adhered by a sealant. Both the first OLED display panel and the second OLED display panel include an open area and a non-open area, and the non-open area is provided with a black matrix.

Abstract: A semiconductor module includes a substrate on which first, second, and third circuit boards that are electrically isolated from each other are formed; a semiconductor element arranged on the first circuit board; a connecting member that bridges an upper surface electrode of the semiconductor element and the second circuit board so as to electrically connect the upper surface electrode to the second circuit board; a wire that electrically connects the third circuit board to a first electrode that is located outside of where the first, second and third circuit boards are located in a plan view; and a sealing resin that covers and seals the substrate, the semiconductor element, the connecting member, and the wire, wherein the wire is wired from the third circuit board to the first electrode so as to cross the semiconductor element at a vertical position lower than an upper surface of the connecting member.

Abstract: Embodiments of the present invention disclose an MRAM cell layout for 32 nm, 45 nm, and 65 nm CMOS process technology.

Abstract: A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.

Abstract: An object is to improve the productivity of a power semiconductor device. A power semiconductor device according to the invention includes a circuit portion having a conductor for transmitting a current and a power semiconductor element, a first base portion and a second base portion facing each other with the circuit portion interposed therebetween, and a transfer mold member which is in contact with the conductor and the power semiconductor element and is filled in a space between the first base portion and the second base portion. The first base portion includes a first flat portion that is connected to a peripheral edge of the first base portion, and a first bent portion that connects the first flat portion and another portion of the first base portion and is plastically deformed. The transfer mold member is integrally configured in contact with the first flat portion.

Abstract: In one example, a semiconductor device includes a substrate with a top side, a bottom side, and a conductive structure. A first electronic component includes a first side, a second side, and first component terminals adjacent to the first side. The first component terminals face the substrate bottom side and are connected to the conductive structure. A second electronic component comprises a first side, a second side, and second component terminals adjacent to the second electronic component first side. The second electronic component second side is connected to the first electronic component second side so that the first component terminals and the second component terminals face opposite directions. Substrate interconnects are connected to the conductive structure, and a bottom encapsulant covers the substrate bottom side, the first electronic component, the second electronic component, and the substrate interconnects.

Abstract: Stacked semiconductor dies for semiconductor device assemblies and associated methods and systems are disclosed. In some embodiments, the semiconductor die assembly includes a substrate with a first opening in an inner portion and a second opening in an outer portion of the substrate. Further, the semiconductor die assembly can include a master die attached to a front side of the substrate, where the master die includes a first bond pad proximate to the first opening and a second bond pad proximate to the second opening. The first and second bond pads of the master die can be coupled with first and second substrate bond pads on a back side of the substrate, opposite to the front side, using first and second bonding wires extending through the first and second openings, respectively.

Abstract: A memory package includes a package substrate including power wiring and ground wiring. The memory package also includes a memory controller disposed over an upper surface of the package substrate and electrically connected to the power wiring and the ground wiring. The memory package further includes a memory chip disposed over the memory controller and electrically connected to the power wiring and the ground wiring. The memory package additionally includes a band pass filter disposed at one side of the memory controller over the upper surface of the package substrate and including an inductor and a capacitor which are connected in series. The inductor and the capacitor connected in series are electrically connected between the power wiring and the ground wiring.

Abstract: A semiconductor die is provided. The semiconductor die includes: at least one complementary metal oxide semiconductor (CMOS) circuit module electrically coupled to at least one memory die, the at least one memory die being separated from the semiconductor die; and a controller module electrically coupled to the CMOS circuit module and configured to control the at least one CMOS circuit module and the at least one memory die. A semiconductor package is also provided.

Abstract: The present application relates to an encapsulation film, a method for producing the same, an organic electronic device comprising the same, and a method for preparing an organic electronic device using the same, which allows forming a structure capable of blocking moisture or oxygen introduced into an organic electronic device from the outside, and can prevent occurrence of bright spots of the organic electronic device.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) including a first fin structure and a second fin structure vertically extending from a semiconductor substrate, respectively. The first fin structure laterally extends along a first direction and has a first width. The second fin structure laterally extends along the first direction and has a second width that is less than the first width. A first plurality of nanostructures directly overlies the first fin structure and is vertically spaced from the first fin structure by a non-zero distance. A gate electrode continuously laterally extends along a second direction that is substantially perpendicular to the first direction. The gate electrode directly overlies the first and second fin structures, and wraps around the nanostructures.

Abstract: A modified perovskite quantum dot material, a fabricating method thereof, and a display device are provided. Hydroxyl-modified perovskite quantum dots are obtained by adding an excess amount of hydroxyl-containing surface ligands to a solution of synthesized perovskite quantum dots. After high-speed centrifugation, the obtained perovskite quantum dots are redispersed into a non-polar alkyl solvent to form a solution. Further, an excess amount of ethyl orthosilicate is added to the solution, and after exposing the solution for a long period of time, the ethyl orthosilicate is hydrolyzed to form a triethoxysilane group. After centrifugation, modified perovskite quantum dots wrapped by the triethoxysilane groups are obtained, which effectively improves stability of the perovskite quantum dots.

Abstract: A semiconductor device, including: a heat sink which has a mounting surface, a heat radiation surface, a side surface and an engagement part, a semiconductor chip which is mounted on the mounting surface of the heat sink, a lead frame which is engaged with the engagement part of the heat sink, and a mold resin which seals the heat sink, the semiconductor chip and the lead frame, wherein the engagement part of the heat sink is disposed at a place which avoids the mounting surface of the heat sink. The engagement part of the heat sink is a dowel formed in the heat radiation surface of the heat sink. Further, the engagement part of the heat sink is a dowel formed in the side surface of the heat sink.

Abstract: A microelectronic package may be fabricated having a microelectronic die stack attached to a microelectronic substrate and at least one microelectronic device, which is separate from the microelectronic die stack, attached to the microelectronic substrate within the footprint of one of the microelectronic dice within the microelectronic die stack. In one embodiment, the microelectronic die stack may have a plurality of stacked microelectronic dice, wherein one microelectronic die of the plurality of microelectronic dice has a footprint greater than the other microelectronic die of the plurality of microelectronic dice, and wherein the at least one microelectronic device is attached to the one microelectronic die of the plurality of microelectronic dice having the greater footprint.