Abstract: A method of forming a semiconductor structure includes forming an opening in a substrate. A dielectric layer is formed and substantially conformal to the opening. A sacrificial structure is formed within the opening, covering a portion of the dielectric layer. A portion of the dielectric layer is removed by using the sacrificial structure as an etch mask layer. The sacrificial structure is removed.

Abstract: A display includes a display panel and an image capture apparatus. The display panel has a display region, a peripheral region surrounding the display region, and a through hole located in the peripheral region. The image capture apparatus is assembled to the display panel. The image capture apparatus includes a signal transmission device and an image capture device located in the through hole, and the image capture device is connected to the signal transmission device.

Abstract: Some embodiments relate to a method for processing a workpiece. In the method, a first photoresist layer is provided over the workpiece, wherein the first photoresist layer has a first photoresist tone. The first photoresist layer is patterned to provide a first opening exposing a first portion of the workpiece. A second photoresist layer is then provided over the patterned first photoresist layer, wherein the second photoresist layer has a second photoresist tone opposite the first photoresist tone. The second photoresist layer is then patterned to provide a second opening that at least partially overlaps the first opening to define a coincidentally exposed workpiece region. A treatment is then performed on the coincidentally exposed workpiece region. Other embodiments are also disclosed.

Abstract: Provided is a lithography system operation to include a first aperture or a second aperture. Each of the first and second apertures has two pairs of radiation-transmitting regions where one pair of radiation-transmitting regions are larger than a second pair. For an aperture, each pair of radiation-transmitting regions are on different diametrical axis. In an embodiment, one aperture is used for x-dipole illumination and the second aperture is used for y-dipole illumination.

Abstract: A fan assembly structure is provided. The fan assembly structure comprises a fan, an air-flow guiding structure and a fixing component. The air-flow guiding structure has a plurality of air-flow guiding holes, a leaning portion and a plurality of first locking portions distributed on the leaning portion. The fixing component has a plurality of second locking portions. The fan is pivotally connected with the fixing component. The second locking portion is adapted to rotate by an angle with respect to the leaning portion to lock with the corresponding first locking portion. Thereby, the fan is disposed on the air-flow guiding structure by only the fixing component.

Abstract: A method for planarizing a semiconductor device includes providing a substrate having at least one opening therein, each opening defining a lower portion and an upper portion; coating a light sensitive material layer over the substrate, the light sensitive material layer covering the lower and upper portions of the at least one opening; etching back the light sensitive material layer to expose the upper portion of the at least one opening; repeating the steps of coating and etching to remove a predetermined amount below the upper portion of the at least one opening; depositing an insulating layer over the substrate; and planarizing the insulating layer until the upper portion of the at least one opening is exposed.

Abstract: Embodiments of the invention describe an enclosure for an image capture system that includes an image capture unit and a solid state die to provide focusing capabilities for a lens unit of the image capture unit. The enclosure may electrically couple the solid state die to the image capture unit and/or other system circuitry. The enclosure may further serve as EMI shielding for the image capture system.

Abstract: A method of forming a semiconductor structure includes forming an opening in a substrate. A dielectric layer is formed and substantially conformal to the opening. A sacrificial structure is formed within the opening, covering a portion of the dielectric layer. A portion of the dielectric layer is removed by using the sacrificial structure as an etch mask layer. The sacrificial structure is removed.

Abstract: Methods and systems for lithographically exposing a substrate based on a curvature profile of the substrate.

Abstract: A hard mask layer and a developable bottom anti-reflective coating (dBARC) layer are formed over a dielectric layer of a substrate. A first photosensitive layer is formed above the dBARC layer, exposed, and developed to form a first pattern. The dBARC layer is developed. The first pattern is etched into the hard mask layer to form a first pattern of openings in the hard mask layer. Following removal of the first photosensitive layer, a second photosensitive layer is formed within the first pattern of openings. The second photosensitive layer is exposed and developed to form a second pattern. The dBARC layer is developed. The second pattern is etched into the hard mask layer to form a second pattern of openings in the hard mask layer. Following the removal of the second photosensitive layer and the dBARC layer, the first and the second patterns are etched into the dielectric layer.

Abstract: A memory device includes an array of dielectric charge trapping structures memory cells including word lines and bit lines. Control circuitry is coupled to the array arranged to control read, program and erase operations. A controller is arranged with supporting circuitry thermally annealing charge trapping structures in the memory cells in the array. Word line drivers and word line termination circuits can be used to induce current flow on the word lines to induce heat for the annealing. The thermal annealing can be applied interleaved with normal operations for recover from cycling damage. Also, the thermally annealing can be applied during mission functions like erase, to improve performance of the function.

Abstract: A method for planarizing a semiconductor device includes providing a substrate having at least one opening therein, each opening defining a lower portion and an upper portion; coating a light sensitive material layer over the substrate, the light sensitive material layer covering the lower and upper portions of the at least one opening; etching back the light sensitive material layer to expose the upper portion of the at least one opening; repeating the steps of coating and etching to remove a predetermined amount below the upper portion of the at least one opening; depositing an insulating layer over the substrate; and planarizing the insulating layer until the upper portion of the at least one opening is exposed.

Abstract: A system for planarizing a semiconductor device includes a holder component for holding the substrate. The substrate has at least one opening therein, and each opening defines a lower portion and an upper portion. A resist applicator applies a layer of resist over the substrate, such that the resist layer covers the lower and upper portions. An etching component etches back the resist layer to expose the upper portion of the at least one opening. The resist applicator and the etching component repeat the steps of applying and etching, respectively, to remove a predetermined amount below the upper portion. A deposition component deposits an insulating layer over the substrate. A planarizing component planarizes the insulating layer until the upper portion of the at least one opening is exposed.

Abstract: An apparatus provides large area atmospheric pressure plasma enhanced chemical vapor deposition without contaminations in its electrode assembly and deposited films. The apparatus consists of a large area vertical planar nitrogen plasma activation electrode assembly and its high voltage power supply, a large area vertical planar nitrogen plasma deposition electrode assembly and its high voltage power supply, a long-line uniform precursor jet apparatus, a roll-to-roll apparatus for substrate movement, and a sub-atmospheric pressure deposition chamber and its pumping apparatus.

Abstract: A method and an apparatus for estimating temperature are provided for estimating a temperature of a test point in a space with an air conditioner. In the method, a first and a second sensor device are deployed in the space, wherein the second sensor device is deployed at the test point. Then, state parameters and temperature transformation functions are defined according to temperatures detected by the first and the second sensor devices and a state of the air conditioner during a predetermined time period. After the second sensor device is removed, a current state of the air conditioner is determined by reference temperatures detected by the first sensor device and the state parameters. One of the temperature transformation functions is selected according to the current state, and a current temperature of the test point is estimated by using the selected temperature transformation function and the reference temperatures.

Abstract: A method for BCI control is utilized to control a plurality of brain control devices. The brain control devices are capable of executing an operation themselves. A brain-wave control platform is provided for supplying a first signal and a second signal, wherein the first and second signals are utilized to visually evoke a user's first and second brain waves, respectively. The brain-wave control platform selects one of the brain control devices as a to-be-controlled device by the first brain wave, and the to-be-controlled device is controlled to finish an operation by the second brain wave.

Abstract: A mask substrate, photomask and method for forming the same are provided. The photomask includes a substantially light transparent substrate and a circuitry pattern disposed over the light transparent substrate. The circuitry pattern includes a phase shifting layer disposed over the substantially light transparent substrate. A substantially light shielding layer is disposed over the phase shifting layer. At least one barrier layer is disposed over the substantially light shielding layer. An uppermost portion of the substantially light shielding layer does not comprise anti-reflective properties and the at least one barrier layer comprises an uppermost hardmask layer and an underlying anti-reflective layer.

Abstract: A transformer is disclosed. The transformer includes a first pin, a second pin, a first side winding, a second side winding, and a jump pin. The second side winding is coupled to the first pin and the second pin. The first pin is between the jump pin and the second pin. The jump pin is coupled to the second pin inside the transformer.

Abstract: Methods and systems for lithographically exposing a substrate based on a curvature profile of the substrate.

Abstract: In a package, a heat slug, encapsulated by molding compound, encases an integrated circuit device (IC). In an example embodiment, a semiconductor package structure comprises a substrate having conductive traces and pad landings. The conductive traces have pad landings. An IC is mounted on the substrate. The IC has bonding pads. With conductive wires, the IC bonding pads are connected to the pad landings, which in turn, are connected to the conductive traces. A heat slug, having predetermined height, is disposed on the substrate surface. The heat slug includes a plurality of mounting feet providing mechanical attachment to the substrate. A cavity in the heat slug accommodates the IC. A plurality of first-size openings surrounds the IC. A second-size opening constructed from one of the first size-openings, is larger than the first-size opening. The second size-opening facilitates the introduction of molding compounds into the cavity of the heat slug.