Abstract: The present disclosure provides a semiconductor device package including a first substrate, a second substrate disposed over the first substrate, an electronic component disposed between the first substrate and the second substrate, a spacer disposed between the first substrate and the electronic component, and a supporting element disposed on the first substrate and configured to support the second substrate. The spacer is configured to control a distance between the first substrate and the second substrate through the electronic component. A method of manufacturing a semiconductor device package is also disclosed.

Abstract: The present disclosure describes a semiconductor structure with a dielectric liner. The semiconductor structure includes a substrate and a fin structure on the substrate. The fin structure includes a stacked fin structure, a fin bottom portion below the stacked fin structure, and an isolation layer between the stacked fin structure and the bottom fin portion. The semiconductor structure further includes a dielectric liner in contact with an end of the stacked fin structure and a spacer structure in contact with the dielectric liner.

Abstract: The present disclosure provides an electronic assembly including a semiconductor device package. The semiconductor device package includes a first package and a conductive element. The first package includes an electronic component and a protection layer covering the electronic component. The conductive element is supported by the protection layer and electrically connected with the electronic component through an electrical contact. A method for manufacturing a semiconductor device package is also provided in the present disclosure.

Abstract: A semiconductor device include: a first bus waveguide; a first silicon ring optically coupled to the first bus waveguide; a backup silicon ring optically coupled to the first bus waveguide; a first heater and a second heater configured to heat the first silicon ring and the backup silicon ring, respectively; and a first switch, where the first switch is configured to electrically couple the first silicon ring to a first radio frequency (RF) circuit when the first switch is at a first switching position, and is configured to electrically couple the backup silicon ring to the first RF circuit when the first switch is at a second switching position.

Abstract: The present disclosure provides a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. The present disclosure also includes forming a trench between neighboring source/drain features to remove bridging between the neighboring source/drain features. In some embodiments, the trenches between the source/drain features are formed by etching from the backside of the substrate.

Abstract: An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor on a substrate. The source/drain regions of the first nanostructure are electrically isolated from the semiconductor substrate by dielectric barriers. The source/drain regions of the second nanostructure transistor in direct contact with the semiconductor substrate.

Abstract: Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.

Abstract: Provided is a memory device including a substrate, a plurality of word-line structures, a plurality of cap structures, and a plurality of air gaps. The word-line structures are disposed on the substrate. The cap structures are respectively disposed on the word-line structures. A material of the cap structures includes a nitride. The nitride has a nitrogen concentration decreasing along a direction near to a corresponding word-line structure toward far away from the corresponding word-line structure. The air gaps are respectively disposed between the word-line structures. The air gaps are in direct contact with the word-line structures. A method of forming a memory device is also provided.

Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.

Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells by chemical reaction. The metal components are then removed by chemical reaction.

Abstract: A biplane flying device includes a fuselage, an upper wing, a lower wing, a first propulsion assembly and a second propulsion assembly. The upper wing is connected to one side of the fuselage. The upper wing has a first end and a second end opposite to each other. The lower wing is connected to the fuselage and opposite to the upper wing. The lower wing has a third end and a fourth end opposite to each other. The first end is opposite to the third end, and the second end is opposite to the fourth end. The first propulsion assembly is connected between the first end, the third end and the fuselage. The second propulsion assembly is connected between the second end, the fourth end and the fuselage.

Abstract: A semiconductor device package and a method for manufacturing the semiconductor device package are provided. The semiconductor device package includes a first substrate with a aperture, a second substrate disposed on the first substrate, a first electronic component disposed on the second substrate, an encapsulant disposed on the first substrate and covering the second substrate and a first heat dissipation structure extending through the aperture and attached to the second substrate.

Abstract: A semiconductor device includes a first fin, a second fin, a first gate electrode having a first portion that at least partially wraps around an upper portion of the first fin and a second portion that at least partially wraps around an upper portion of the second fin, a second gate electrode having a portion that at least partially wraps around the upper portion of the first fin, and a gate-cut feature having a first portion in the first gate electrode between the first and second portions of the first gate electrode. The gate-cut feature is at least partially filled with one or more dielectric materials. In a direction of a longitudinal axis of the first fin, the gate-cut feature has a second portion extending to a sidewall of the second gate electrode.

Abstract: An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor on a substrate. The source/drain regions of the first nanostructure are electrically isolated from the semiconductor substrate by bottom dielectric regions. The source/drain regions of the second nanostructure transistor in direct contact with the semiconductor substrate.

Abstract: An image recognition system includes a processing module, a sensor module, and a database. The sensor module is electrically connected to the processing module. The database is electrically connected to the processing module. The sensor module configured for capturing at least one image. The at least one image is stored in the database. The processing captures a contour of an object from the at least one image and separates the contour of the object into a plurality of portions. A plurality of arrangements is defined between the portions of the contour of the object. The processing module determines a state of the contour of the object based on the arrangements.

Abstract: A device includes a substrate, a first semiconductor channel over the substrate, and a second semiconductor channel over the substrate and laterally separated from the first semiconductor channel. A gate structure covers and wraps around the first semiconductor channel and the second semiconductor channel. A first source/drain region abuts the first semiconductor channel on a first side of the gate structure, and a second source/drain region abuts the second semiconductor channel on the first side of the gate structure. An isolation structure is under and between the first source/drain region and the second source/drain region, and includes a first isolation region in contact with bottom surfaces of the first and second source/drain regions, and a second isolation region in contact with sidewalls of the first and second source/drain regions, and extending from a bottom surface of the first isolation region to upper surfaces of the first and second source/drain regions.

Abstract: An automatic detection circuit for an integrated circuit and an automatic detection method for the same are provided. The automatic detection circuit is suitable for a system-on-chip (SoC). A control unit of the automatic detection circuit enters an automatic detection mode to: switch a first dynamic switching circuit to connect a main bus to a virtual host circuit; switch a second dynamic switching circuit to connect memory interfaces and intellectual property circuit to a virtual input and output circuit; send detection vectors to the virtual host circuit to set and activate the memory interfaces and the intellectual property circuits; send the detection vectors to the virtual I/O circuit to replace external memory and external equipment for sending and receiving signals; and compare signals received by the virtual host circuit or signals received by the virtual input and output circuit with predetermined signal data to generate a detection result.

Abstract: The disclosure is a linear actuator. A transmission mechanism includes a motor, a gear set and a screw rod. A releasing mechanism is disposed between the gear set and the screw rod and includes a driving gear, a first clutch, a second clutch and a sliding sleeve. A toggle restraining mechanism includes a stem, a rotating element and a restraining assembly. The rotating element has a restraining hole and a rotating arm. The restraining assembly includes a restraining presser, a restraining spring and an engaging element. The stem is moved to rotate the rotating element, the rotating arm is rotated with the rotating element to push the sliding sleeve. The sliding sleeve is pushed by the rotating arm to separate from the second clutch. The engaging element is engaged in the restraining hole to restrain the rotating element from rotating when the rotating element is rotated to a specific angle.

Abstract: The invention uses intestinal microbial flora and combinations thereof as a liver cancer biomarker and provide a method for detection, in short, the intestinal microbial flora of the invention can be used as a liver cancer biomarker and can be used as a non-invasive method for detecting or predicting liver cancer, combined with conventional blood tests, not only capable of improving the accuracy rate of detection, but also capable of increasing the willingness of patients to participate in detection to achieve the efficacies of early prevention and early treatment.

Abstract: The present disclosure provides a photo sensing device, the photo sensing device includes a substrate, including a silicon layer at a front surface, a photosensitive member extending into and at least partially surrounded by the silicon layer, a first doped region having a first conductivity type at a first side of the photosensitive member, wherein the first doped region is in the silicon layer, and a second doped region having a second conductivity type different from the first conductivity type at a second side of the photosensitive member opposite to the first side, wherein the second doped region is in the silicon layer, and the first doped region is apart from the second doped region, and a superlattice layer disposed between the photosensitive member and the silicon layer, wherein the superlattice layer includes a first material and a second material different from the first material.