Abstract: A semiconductor device package includes a main substrate, at least one thin film transistor (TFT) module, at least one first electronic component, at least one encapsulant and a plurality of light emitting devices. The main substrate has a first surface and a second surface opposite to the first surface. The thin film transistor (TFT) module is disposed adjacent to and electrically connected to the first surface of the main substrate. The first electronic component is disposed adjacent to and electrically connected to the first surface of the main substrate. The encapsulant covers the at least one thin film transistor (TFT) module and the at least one first electronic component. The light emitting devices are electrically connected to the at least one thin film transistor (TFT) module.

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a first semiconductor channel member and a second semiconductor channel member extending between the first and second source/drain features, and a first dielectric feature and a second dielectric feature each including a first dielectric layer and a second dielectric layer different from the first dielectric layer. The first and second dielectric features are sandwiched between the first and second semiconductor channel members.

Abstract: Provided are an air cell device and an air mattress system thereof. The air cell device includes an air cell which has therein an upper connection segment and a lower connection segment. The upper connection segment and the lower connection segment each have a curved portion whereby the air cell is partitioned to become a multilayered air cell so as to mitigate air cell bending or air cell inversion, thereby improving the lying human being's comfort.

Abstract: A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.

Abstract: A semiconductor package includes a substrate, a semiconductor device, and a ring structure. The semiconductor device disposed on the substrate. The ring structure disposed on the substrate and surrounds the semiconductor device. The ring structure includes a first portion and a second portion. The first portion bonded to the substrate. The second portion connects to the first portion. A cavity is between the second portion and the substrate.

Abstract: An optical device for coupling light propagating between a waveguide and an optical transmission component is provided. The optical device includes a taper portion and a grating portion. The taper portion is disposed between the grating portion and the waveguide. The grating portion includes rows of grating patterns. A first size of a first grating pattern in a first row of grating patterns is larger than a second size of a second grating pattern in a second row of grating patterns. A first distance between the first row of grating patterns and the waveguide is less than a second distance between the second row of grating patterns and the waveguide.

Abstract: A method and a system for recording an integrated circuit version are provided. The method is adapted to a register in an integrated circuit, which includes the following steps: recording the integrated circuit version with N bits, in which N is an integer greater than 1; and amending only a bit value of at least one bit selected from the N bits that have not been used for denoting any past integrated circuit version each time when the integrated circuit is revised.

Abstract: A system for poisoned data management includes an interface and a processor. The interface is configured to receive an indication of poisoned data in a published event. The processor is configured to mark the poisoned data in a data graph; mark in the data graph a set of downstream nodes as poisoned; and store the data graph.

Abstract: An integrated substrate for an anti-shake apparatus defined with an optical axis includes: a substrate, a lens module, an anti-shake apparatus and an image-sensing module. The substrate includes a frame having, a predetermined thickness. The frame includes a first surface, a second surface, a first circuit layout, and a second circuit layout. The lens module is located above the substrate on the optical axis. The anti-shake apparatus is furnished between the lens module and the substrate. The image-sensing module has an active side and an inactive side, and the inactive side is furnished onto the second surface. The active side is located on the optical axis in a manner of facing the lens module. The anti-shake apparatus is coupled to the first circuit layout, while the image-sensing module is coupled to the second circuit layout. The first and second circuit layouts comprise a plurality of first and second metal leads, respectively.

Abstract: Provided is a memory device including a substrate, a plurality of word-line structures, a plurality of cap structures, and a plurality of air gaps. The word-line structures are disposed on the substrate. The cap structures are respectively disposed on the word-line structures. A material of the cap structures includes a nitride. The nitride has a nitrogen concentration decreasing along a direction near to a corresponding word-line structure toward far away from the corresponding word-line structure. The air gaps are respectively disposed between the word-line structures. The air gaps are in direct contact with the word-line structures. A method of forming a memory device is also provided.

Abstract: A method of forming a semiconductor device includes forming a fin of alternating layers of semiconductor nanostructures and sacrificial layers, laterally etching sidewall portions of the sacrificial layers, and depositing additional semiconductor material over the sidewalls of the semiconductor nanostructures and sacrificial layers. Following deposition of a dielectric material over the additional semiconductor material and additional etching, the remaining portions of the semiconductor structures and additional semiconductor material collectively form a hammer shape at each opposing side of the fin. Epitaxial source/drain regions formed on the opposing sides of the fin will contact the heads of the hammer shapes.

Abstract: An image recognition system includes a processing module, a sensor module, and a database. The sensor module is electrically connected to the processing module. The database is electrically connected to the processing module. The sensor module configured for capturing at least one image. The at least one image is stored in the database. The processing captures a contour of an object from the at least one image and separates the contour of the object into a plurality of portions. A plurality of arrangements is defined between the portions of the contour of the object. The processing module determines a state of the contour of the object based on the arrangements.

Abstract: A power rail design method is disclosed that includes the steps outlined below. A plurality of power rails and a plurality of power domains corresponding thereto in an integrated circuit design file are identified. A design rule check for a plurality of circuit units in the integrated circuit design file is performed to retrieve a plurality of non-violating circuit regions that correspond to the power rails in each of the power domains. The power rails corresponding to at least part of the plurality of non-violating circuit regions in the integrated circuit design file are widened to occupy at least part of the non-violating circuit regions for the plurality of power rails.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor fin projecting from a substrate. Semiconductor nanostructures are disposed over the semiconductor fin. A gate electrode is disposed over the semiconductor fin and around the semiconductor nanostructures. A dielectric fin is disposed over the substrate. A dielectric structure is disposed over the dielectric fin. An upper surface of the dielectric structure is disposed over the upper surface of the gate electrode. A dielectric layer is disposed over the substrate. The dielectric fin laterally separates both the gate electrode and the semiconductor nanostructures from the dielectric layer. An upper surface of the dielectric layer is disposed over the upper surface of the gate electrode structure and the upper surface of the dielectric structure. A lower surface of the dielectric layer is disposed below the upper surface of the dielectric fin.

Abstract: A semiconductor structure includes a semiconductor device, a plurality of through semiconductor vias (TSV), a first seal ring, and a second seal ring. The TSVs are in the semiconductor device. Each of the TSVs has a first surface and a second surface opposite to the first surface. The first seal ring is located in proximity to an edge of the semiconductor structure and is physically connected to the first surface of each of the TSVs. The second seal ring is physically connected to the second surface of each of the TSVs.

Abstract: A semiconductor package device includes a first substrate, a second substrate and a first spacer. The first substrate includes a first divided pad. The second substrate includes a second divided pad disposed above the first divided pad. The first spacer is disposed between the first divided pad and the second divided pad. The first spacer is in contact with the first divided pad and the second divided pad.

Abstract: A device includes a substrate, a semiconductor layer, a gate structure, source/drain regions, a bottom isolation layer, and a bottom spacer. The semiconductor layer is above the substrate. The gate structure is above the substrate and surrounds the semiconductor layer. The source/drain regions are on opposite sides of the semiconductor layer. The bottom isolation layer is between the substrate and the semiconductor layer. The bottom spacer is on a sidewall of the bottom isolation layer. The bottom isolation layer has a seam therein, and the seam exposes a sidewall of the bottom spacer.

Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.

Abstract: A harmonic speed reducer is provided. The harmonic speed reducer includes a wave generator, a flexible gear, a first rigid gear, and a second rigid gear. The wave generator can be driven to rotate relative to a central axis. The flexible gear has a plurality of first outer gear structures, a division groove, and a plurality of second outer gear structures. The first rigid gear has a plurality of first inner gear structures configured to be engaged with the first outer gear structures. The second rigid gear has a plurality of second inner gear structures configured to be engaged with the second outer gear structures. A first intersection line is defined between each of the first inner gear structures and a sectional surface. An angle between the first intersection line and a first horizontal line is within a range from 0.1 degrees to 5 degrees.

Abstract: Systems, devices, and methods related to Video Surveillance as a Service (VSaaS) are described. For example, a removable storage device, such as a secure digital (SD) memory card or a micro SD card, can be configured to run a virtual camera agent. When the removable storage device is inserted into a digital camera to provide a storage capacity for the digital camera, the agent can convert the video captured by the digital camera into video captured by a virtual camera. The virtual camera can be configured to be in compliance with the camera requirements of a VSaaS platform. Thus, a digital camera not in compliance with the platform can still be used with the platform through the deployment of the virtual camera that is enabled by the removable storage device.