Abstract: A manufacturing method of an electronic apparatus is provided, and the manufacturing method includes following steps. A substrate is provided. A plurality of first bonding pads are formed on the substrate. A plurality of electronic devices are provided, and each of the electronic devices includes at least one second bonding pad. The second bonding pads of the electronic devices corresponding to the first bonding pads are laminated onto the corresponding first bonding pads on the substrate, so as to bond the electronic devices to the substrate. The corresponding first and second bonding pads respectively have bonding surfaces with different surface topographies. The manufacturing method of the electronic apparatus is capable of reducing short circuit during a bonding process or improving a bonding yield.

Abstract: Embodiments of the present disclosure relate to an un-doped or low-doped epitaxial layer formed below the source/drain features. The un-doped or low-doped epitaxial layer protects the source/drain features from damage during replacement gate processes, and also prevent leakage currents in the mesa device. A semiconductor device is disclosed. The semiconductor device includes an epitaxial feature having a dopant of a first concentration, and a source/drain feature in contact with the epitaxial feature. The source/drain feature comprises the dopant of a second concentration, and the second concentration is higher than the first concentration.

Abstract: A method of forming a semiconductor device includes forming a fin of alternating layers of semiconductor nanostructures and sacrificial layers, laterally etching sidewall portions of the sacrificial layers, and depositing additional semiconductor material over the sidewalls of the semiconductor nanostructures and sacrificial layers. Following deposition of a dielectric material over the additional semiconductor material and additional etching, the remaining portions of the semiconductor structures and additional semiconductor material collectively form a hammer shape at each opposing side of the fin. Epitaxial source/drain regions formed on the opposing sides of the fin will contact the heads of the hammer shapes.

Abstract: A semiconductor device includes a substrate, a first source/drain feature and a second source/drain feature over the substrate, a first semiconductor layer and a second semiconductor layer between the first and the second source/drain features, and a gate between the first and the second source/drain features. A portion of the gate is further between the first and the second semiconductor layers. Moreover, the semiconductor device includes a first inner spacer and a second inner spacer. The first inner spacer is between the first and the second semiconductor layers and further between the portion of the gate and a portion of the first source/drain feature. Furthermore, the portion of the first source/drain feature is between the first semiconductor layer and the second semiconductor layer. The first inner spacer has a U-shaped profile. Additionally, the second inner spacer is between the first inner spacer and the portion of the first source/drain feature.

Abstract: A nanoFET transistor includes doped channel junctions at either end of a channel region for one or more nanosheets of the nanoFET transistor. The channel junctions are formed by a iterative recessing and implanting process which is performed as recesses are made for the source/drain regions. The implanted doped channel junctions can be controlled to achieve a desired lateral straggling of the doped channel junctions.

Abstract: A semiconductor package device includes a substrate, an electronic component, and a thermal conductive layer. The electronic component is disposed on the substrate and includes a first surface facing away from the substrate. The thermal conductive layer is disposed above the first surface of the electronic component. The thermal conductive layer includes a plurality of portions spaced apart from each other.

Abstract: A signal processor includes a signal receiving circuit, a pre-processing circuit, a period acquisition circuit, and a decoding circuit. The signal receiving circuit is configured to receive an input signal. The pre-processing circuit is configured to generate a square wave signal according to the input signal. The period acquisition circuit is configured to capture several periods of the square wave signal. The several signal periods includes several signal period groups, and each of the several signal period groups includes at least two signal periods of the several signal periods. The at least two signal periods are adjacent to each other. The decoding circuit is coupled to the period acquisition circuit and is configured to perform decoding according to a time length and a number of times of voltage value change of the several signal period groups to obtain a decoding result.

Abstract: Disclosed is an IC voltage determining method including: executing a static timing analysis according to a circuit design to obtain data of a critical path and then generating a netlist; executing a circuit parameter simulation and Monte Carlo simulation with the netlist according to a regular voltage and prescribed parameters to obtain a circuit parameter reference value and a variance of circuit parameter values; executing an adaptive voltage scaling analysis according to a voltage range to obtain a voltage-versus-parameter relation indicative of the number of times that each of circuit parameter deviations that are respectively associated with predetermined voltages within the predetermined voltage range is of the variance; and testing an IC according to the regular voltage to obtain a circuit parameter test value and determining the IC voltage according to the voltage-versus-parameter relation and a difference between the circuit parameter test value and the circuit parameter reference value.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method includes forming a bottom electrode layer over a substrate and forming a pinned layer over the bottom electrode layer. The method also includes forming a tunnel barrier layer over the pinned layer and forming a free layer over the tunnel barrier layer. The method also includes patterning the free layer, the tunnel barrier layer, and the pinned layer to form a magnetic tunnel junction (MTJ) stack structure and patterning the bottom electrode layer to form a bottom electrode structure under the MTJ stack structure. In addition, patterning the free layer includes using a first etching gas, and patterning the bottom electrode layer includes using a second etching gas, which is different from the first etching gas.

Abstract: The present disclosure provides a method of forming a semiconductor structure with a metal gate. The semiconductor structure is formed by first fabricating fins over a semiconductor substrate, followed by a formation of a source and a drain recess. A source and a drain region may then be deposited into the source and the drain recess. The gate structure may be deposited into the region between the fins. The gate structure includes dielectric and metallic layers. In the regions between the fins, the gate structure is isolated from the source and the drain region by an insulating layer.

Abstract: Semiconductor devices using a dielectric structure and methods of manufacturing are described herein. The semiconductor devices are directed towards gate-all-around (GAA) devices that are formed over a substrate and are isolated from one another by the dielectric structure. The dielectric structure is formed over the fin between two GAA devices and cuts a gate electrode that is formed over the fin into two separate gate electrodes. The two GAA devices are also formed with bottom spacers underlying source/drain regions of the GAA devices. The bottom spacers isolate the source/drain regions from the substrate. The dielectric structure is formed with a shallow bottom that is located above the bottoms of the bottom spacers.

Abstract: Disclosed is a detecting method of a wearable device, which comprises: providing a current to drive a light source to emit auxiliary light corresponding to ambient light received by the wearable device; and informing a wearing status indicative whether the wearable device is correctly worn by a user or not according to the current. By this way, the wearing status of the user can be easily detected.

Abstract: A finFET device and methods of forming a finFET device are provided. The method includes depositing a dummy gate over and along sidewalls of a fin extending upwards from a semiconductor substrate, forming a first gate spacer along a sidewall of the dummy gate, and plasma-doping the first gate spacer with carbon to form a carbon-doped gate spacer. The method further includes forming a source/drain region adjacent a channel region of the fin and diffusing carbon from the carbon-doped gate spacer into a first region of the fin to provide a first carbon-doped region. The first carbon-doped region is disposed between at least a portion of the source/drain region and the channel region of the fin.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.

Abstract: An optical device for coupling light propagating between a waveguide and an optical transmission component is provided. The optical device includes a taper portion and a grating portion. The taper portion is disposed between the grating portion and the waveguide. The grating portion includes rows of grating patterns. A first size of a first grating pattern in a first row of grating patterns is larger than a second size of a second grating pattern in a second row of grating patterns. A first distance between the first row of grating patterns and the waveguide is less than a second distance between the second row of grating patterns and the waveguide.

Abstract: The disclosure is a linear actuator. A transmission mechanism includes a motor, a gear set and a screw rod. A releasing mechanism is disposed between the gear set and the screw rod and includes a driving gear, a first clutch, a second clutch and a sliding sleeve. A toggle restraining mechanism includes a stem, a rotating element and a restraining assembly. The rotating element has a restraining hole and a rotating arm. The restraining assembly includes a restraining presser, a restraining spring and an engaging element. The stem is moved to rotate the rotating element, the rotating arm is rotated with the rotating element to push the sliding sleeve. The sliding sleeve is pushed by the rotating arm to separate from the second clutch. The engaging element is engaged in the restraining hole to restrain the rotating element from rotating when the rotating element is rotated to a specific angle.

Abstract: The disclosure is a nut structure for an electric pushing rod. The electric pushing rod has a guide screw (A) with an outer thread (A1). The nut structure includes a metal cylinder (10) and a plastic intermediate component (20). The metal cylinder (10) has a pivot hole (11) being passed through by the guide screw (A). An inner wall of the pivot (11) is provided with an inner thread (12). The plastic intermediate component (20) covers the inner thread (12) and is disposed of between the outer thread (A1) and the inner thread (12). The plastic intermediate component (20) includes a fixed side thread (21) mounted on the inner thread (12) and a driving side thread (22) screwed with the outer thread (A1). Therefore, the strength may be enhanced to avoid both the nut structure from being broken and the driving side thread (22) from getting stripped.

Abstract: A card connector includes a transmission conductor assembly. The transmission conductor assembly includes a first conductor group and a second conductor group. The first conductor group includes a backup transmission conductor, first and second signal transmission conductors, an inspection signal transmission conductor, first to seventh grounding transmission conductors, a command reset transmission conductor, first to sixth differential transmission conductors, first and second power transmission conductors, and a write-protection transmission conductor, each of which has two ends respectively forming a spring section and a soldering section. The second conductor group includes eighth to tenth grounding transmission conductors, seventh to tenth differential transmission conductors, and a third power transmission conductor each of which has two ends respectively forming a spring section and a soldering section.

Abstract: A display device includes a substrate, a light-emitting element, and a transistor. The substrate has a top surface. The light-emitting element is disposed on the substrate, and includes a first electrode and a second electrode. The transistor is disposed on the substrate and electrically connected to the light-emitting element. The transistor includes a gate electrode and a semiconductor layer. The semiconductor layer includes an overlapping portion overlapped with the gate electrode. The first electrode and the second electrode of the light-emitting element do not overlap with the overlapping portion along a direction perpendicular to the top surface of the substrate.