Abstract: A lifting device with a cable management is provided. The lifting device includes: an outer pipe, an actuation mechanism, a linkage member, a cable, and a cable management component. The actuation mechanism is accommodated in the outer pipe and has a motor and a screw rod. The linkage member is accommodated in the outer pipe and mutually screw-fitted with the screw rod to operate, and moves relative to the outer pipe. The cable has a spiral coiled cable unit. A shaft core line in parallel with the screw rod is defined by the spiral coiled cable unit. The cable management component is disposed in the outer pipe and in parallel to the shaft core line. The spiral coiled cable unit is reeled on the cable management component. Accordingly, the cable may be stably positioned and the cable may be prevented from rubbing or being tangled with the screw rod.

Abstract: A semiconductor device includes a first device formed over a substrate. The first device includes a first device formed over a substrate, and the first device includes a first gate stack structure encircling a plurality of first nanostructures. The semiconductor device includes a first epitaxy structure wrapping an end of one of the first nanostructures, and a second device formed over the first device, wherein the second device includes a second gate stack structure encircling a plurality of second nanostructures. The semiconductor device includes a second epitaxy structure wrapping an end of one of the second nanostructures, and the second epitaxy structure is directly above the first epitaxy structure.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises alternately forming first semiconductor layers and second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers include different materials and are stacked up along a direction substantially perpendicular to a top surface of the substrate; forming a dummy gate structure over the first and second semiconductor layers; forming a source/drain (S/D) trench along a sidewall of the dummy gate structure; forming inner spacers between edge portions of the first semiconductor layers, wherein the inner spacers are bended towards the second semiconductor layers; and epitaxially growing a S/D feature in the S/D trench, wherein the S/D feature contacts the first semiconductor layers and includes facets forming a recession away from the inner spacers.

Abstract: An ultrasonic imaging device includes an ultrasonic generating unit and an ultrasonic imaging processing unit. The ultrasonic generating unit repeatedly turns on N of M ultrasonic array elements of the ultrasonic probe multiple times as a group of array elements for linear scanning, and each scan is to emit an ultrasonic signal by each group of array elements and receive an echo signal of the ultrasonic signal. The ultrasonic imaging processing unit extracts a central echo signal from the echo signal in each scan to form a channel signal, and according to the arrival time of the echo signals, each central echo signal in the channel signal is delayed and summed to generate a modified channel signal. The modified channel signal is subjected to image synthesis process to obtain an ultrasonic image.

Abstract: Systems, devices, and methods related to phase shifters are provided. An example true time-delay (TTD) phase shifter structure includes a signal conductive line disposed on a first layer of the structure; a first switchable ground plane comprising a first conductive plane disposed on a second layer of the structure; a second switchable ground plane comprising a second conductive plane disposed on a third layer of the structure, where the first, second, and third layers are separate layers of the structure; a first switch coupled between the first switchable ground plane and a first ground element, the first ground element disposed on the second layer; and a second switch coupled between the second switchable ground plane and a second ground element, the second ground element disposed on the third layer.

Abstract: A propulsion device includes a propulsion body and a diversion assembly. The propulsion body includes a propulsion system and a housing accommodating the propulsion system. The housing has an air-intake opening and an air-discharge opening respectively on two opposite sides of the propulsion system. The diversion assembly includes first and second diversion annular sheets. The first diversion annular sheet is disposed outside the air-discharge opening of the housing and having a surrounding center. The first diversion annular sheet is swung relative to the air discharge opening by a first axis passing through the surrounding center. The second diversion annular sheet is disposed outside the air-discharge opening of the housing and concentrically disposed with the first diversion annular sheet. The second diversion annular sheet is swung relative to the air-discharge opening by a second axis passing through the surrounding center, and first axis intersects the second axis.

Abstract: The present disclosure provides a photo sensing device, the photo sensing device includes a substrate, including a silicon layer at a front surface, a photosensitive member extending into and at least partially surrounded by the silicon layer, and a superlattice layer disposed between the photosensitive member and the silicon layer, wherein the superlattice layer includes a first material and a second material different from the first material, a first concentration of the second material at a portion of the superlattice layer proximal to the photosensitive member is greater than a second concentration of the second material at a portion of the superlattice layer distal to the photosensitive member.

Abstract: A semiconductor package includes a substrate having a first side and a second side opposite to the first side, a first type semiconductor die disposed on the first side of the substrate, a first compound attached to the first side and encapsulating the first type semiconductor die, and a second compound attached to the second side, causing a stress with respect to the first type semiconductor die in the first compound. A method for manufacturing the semiconductor package described herein is also disclosed.

Abstract: A method for manufacturing a resistor is described. First and second division lines are formed in a first surface of a substrate to define device areas. First and second electrodes are formed on the first surface and respectively on the device areas. Third electrodes, fourth electrodes, and resistive layers are formed on a second surface of the substrate and respectively on the device areas. The substrate is diced from the second surface by a cutting tool to form bar structures to expose opposite first and second side surfaces of the device areas. First and second terminal electrodes are formed to respectively cover the first and second side surfaces. The bar structures are diced from the second surface by the cutting tool to separate the device areas. The cutting tool is aligned with the first and second division lines respectively while dicing the substrate and the bar structures.

Abstract: The present invention provides a circuit within a switch, wherein the circuit includes a memory and a control circuit. The memory includes at least a first area and a second area, the first area is used to provide a minimum guaranteed storage space for each of a plurality of egress queues, the second area is used to provide a shared space of the plurality of egress queues. The control circuit is coupled to the memory, and when an input port of the switch receives an input packet and stores the input packet into the memory, the control circuit dynamically determines a size of the second area according to a number of the egress queues that the input packet is forwarded to.

Abstract: The disclosure provides a light emitting device and a manufacturing method thereof. The light emitting device includes a substrate, a light emitting element, and a bonding structure. The light emitting element is disposed on the substrate through the bonding structure. The bonding structure includes at least three bonding layers and at least two passivation layers, which are in a staggered arrangement. The method for manufacturing the light emitting device includes the following steps: providing a substrate, forming a first bonding layer on the substrate, forming a first passivation layer on the first bonding layer, providing a light emitting element, forming a second bonding layer on the light emitting element, forming a second passivation layer on the second bonding layer. The second passivation layer on the light emitting element is contacted with the first passivation layer to form a third bonding layer and bond the light emitting element on the substrate.

Abstract: A semiconductor device according to the present disclosure includes a stack of first channel members, a stack of second channel members disposed directly over the stack of first channel members, a bottom source/drain feature in contact with the stack of the first channel members, a separation layer disposed over the bottom source/drain feature, a top source/drain feature in contact with the stack of second channel members and disposed over the separation layer, and a frontside contact that extends through the top source/drain feature and the separation layer to be electrically coupled to the bottom source/drain feature.

Abstract: Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.

Abstract: A method for forming a semiconductor device. A substrate having a first region and a second region surrounding the first region is provided. The first region includes a first active area and a first gate. A dummy pattern is disposed on the substrate within the second region around a perimeter of the first region. A resist pattern masks the second region and includes an opening that exposes the first region. An ion implantation process is performed to implant dopants through the opening into the first active area not covered by the first gate within the first region, thereby forming doped regions in the first active area. A resist stripping process is performed to remove the resist pattern by using a sulfuric acid-hydrogen peroxide mixture (SPM) solution at a temperature that is higher than or equal to 120˜190 degrees Celsius. The substrate is subjected to a cleaning process.

Abstract: Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.

Abstract: Disclosed is a time-division multiplexing (TDM) scheduler capable of determining a service order for serving N packet transmission requesters. The TDM scheduler includes: N current count value generators configured to serve the N packet transmission requesters respectively, and generate N current count values according to parameters of the N packet transmission requesters, a previous scheduling result generated by the EDD scheduler previously, and a predetermined counting rule; and an earliest due date (EDD) scheduler configured to generate a current scheduling result for determining the service order according to the N current count values and a predetermined urgency decision rule, wherein an extremum of the N current count values relates to one of the N packet transmission requesters, and the EDD scheduler selects this requester as the one to be served preferentially.

Abstract: An electric push rod with a dual brake mechanism includes an electric motor, a transmission device, a first brake mechanism and a second brake mechanism. The electric motor has a driving wheel. The transmission device is installed on a side of the electric motor and includes a deceleration mechanism, a lead screw, a driven wheel, and a telescopic pipe. The deceleration mechanism is disposed between the driving wheel and the driven wheel. The lead screw is sheathed with the driven wheel and the driven wheel is driven by the electric motor to rotate together with the lead screw. The telescopic pipe and the lead screw are screwed and driven. The lead screw is sheathed with the first brake mechanism formed on a side edge of the driven wheel. The lead screw is sheathed with the second brake mechanism disposed between the driven wheel and the telescopic pipe.

Abstract: An electronic device and a manufacturing method thereof are disclosed. The manufacturing method of the electronic device includes following steps: providing a substrate; forming a first compressible layer on the substrate; forming a first bonding pad on the first compressible layer; providing an electronic component; forming a second bonding pad on the electronic component; and bonding the electronic component with the substrate by contacting the second bonding pad with the first bonding pad.

Abstract: The present disclosure describes an inner spacer structure for a semiconductor device and a method for forming the same. The method for forming the inner spacer structure in the semiconductor device can include forming a vertical structure over a substrate, forming a gate structure over a portion of the vertical structure, exposing sidewalls of the portion of the vertical structure, forming multiple spacers over the sidewalls of the portion of the vertical structure, and forming a void in each of the multiple spacers.