Abstract: A method for manufacturing a semiconductor device includes forming a source layer on a semiconductor substrate, forming a channel layer on the source layer, and forming a drain layer on the channel layer. The source, channel and drain layers are patterned into at least one fin, and a cap layer is formed on a lower portion of the at least one fin. The lower portion of the at least one fin includes the source layer and part of the channel layer. The method further includes forming a gate structure comprising a gate dielectric layer and a gate conductor on the at least one fin and on the cap layer. The cap layer is positioned between the lower portion of the at least one fin and the gate dielectric layer.

Abstract: A robotic device, including a tangible, non-transitory, machine readable medium storing instructions that when executed by a processor effectuates operations including: capturing, with the camera, one or more images of an environment of the robotic device; capturing, with the plurality of sensors, sensor data of the environment; generating or updating, with the processor, a map of the environment; identifying, with the processor, one or more rooms in the map; receiving, with the processor, one or more multidimensional arrays including at least one parameter that is used to identify a feature included in the one or more images; determining, with the processor, a position and orientation of the robotic device relative to the feature; and transmitting, with the processor, a signal to the processor of the controller to adjust a heading of the robotic device.

Abstract: Devices and methods are provided for forming single diffusion break isolation structures for integrated circuit devices including gate-all-around FET devices such as nanosheet FET devices and nanowire FET devices. For example, a semiconductor integrated circuit device includes first and second gate-all-around field-effect transistor devices disposed in first and second device regions, respectively, of a semiconductor substrate. A single diffusion break isolation structure is disposed between the first and second device regions. The single diffusion break isolation structure includes a dummy gate structure disposed on the semiconductor substrate between a first source/drain layer of the first gate-all-around field-effect transistor device and a second source/drain layer of the second gate all-around field-effect transistor device. The single diffusion break isolation structure is configured to electrically isolate the first and second source/drain layers.

Abstract: Provided is a tangible, non-transitory, machine readable medium storing instructions that when executed by one or more processors of a robotic device effectuate operations including capturing, with a camera of the robotic device, spatial data of surroundings of the robotic device; generating, with the one or more processors of the robotic device, a movement path based on the spatial data of the surroundings; capturing, with at least one sensor of the robotic device, at least one measurement relative to the surroundings of the robotic device; obtaining, with the one or more processors of the robotic device, the at least one measurement; and inferring, with the one or more processors of the robotic device, a location of the robotic device based on the at least one measurement.

Abstract: Embodiments of the present application provide a vascular plaque extraction apparatus and method. The method includes: acquiring a computed tomography angiography (CTA) image; performing preprocessing on the CTA image; performing a vascular lumen segmentation on the preprocessed CTA image to obtain a vascular lumen image; performing a dilation operation on the vascular lumen image to obtain a dilated region of interest (ROI), and performing a voxel-based radiomics feature extraction on the dilated ROI to obtain at least one voxel feature map; and extracting vascular plaques based on a preset threshold corresponding to the at least one voxel feature map and the at least one voxel feature map. According to the embodiments of the present application, the vascular plaques can be quickly and accurately extracted from the CTA image, providing a reference for an accurate quantitative analysis and auxiliary diagnosis and treatment.

Abstract: A compound as shown in general formula (I) or stereoisomers, deuterated compounds, solvates, prodrugs, metabolites, pharmaceutically acceptable salts or co-crystals thereof, and intermediates thereof, a preparation method therefor, and a use thereof for treating BTK-related diseases, such as cancer or autoimmune diseases.

Abstract: A method for determining a likelihood that an assist feature of a mask pattern will print on a substrate. The method includes obtaining (i) a plurality of images of a pattern printed on a substrate and (ii) variance data the plurality of images of the pattern; determining, based on the variance data, a model configured to generate variance data associated with the mask pattern; and determining, based on model-generated variance data for a given mask pattern and a resist image or etch image associated with the given mask pattern, the likelihood that an assist feature of the given mask pattern will be printed on the substrate. The likelihood can be applied to adjust one or more parameters related to a patterning process or a patterning apparatus to reduce the likelihood that the assist feature will print on the substrate.

Abstract: Embodiments of the present disclosure provide a broadcasting method and device for a live broadcast, where the method includes: receiving push information of a target creation sent by a server, where the push information is sent by the server when determining that play popularity of the target creation meets preset popularity; and in response to an operation of a user on the push information, entering a broadcasting page of a live broadcast application (App). In the embodiment of the present disclosure, by pushing the target creation whose play popularity exceeds preset popularity to the user, to prompt the user that one target creation is becoming a hot creation, so as to guide the user to carry out a live broadcast with the target creation as a topic.

Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having defect free channels. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating first sacrificial layers and second sacrificial layers. One layer of the first sacrificial layers has a greater thickness than the remaining first sacrificial layers. The first sacrificial layers are removed and semiconductor layers are formed on surfaces of the second sacrificial layers. The semiconductor layers include a first set and a second set of semiconductor layers. The second sacrificial layers are removed and an isolation dielectric is formed between the first set and the second set of semiconductor layers.

Abstract: A method of fabricating a semiconductor device is described. The method includes forming a nanosheet stack on a substrate, the nanosheet stack includes nanosheet channel layers. A gate is formed around the nanosheet channel layers of the nanosheet stack. A strained material is formed along a sidewall surface of the gate. The strained material is configured to create strain in the nanosheet channel layers of the nanosheet stack.

Abstract: A semiconductor device includes a FinFET fin. The same FinFET fin is associated with a bottom FinFET and a top FinFET. The FinFET fin includes a lower channel portion, associated with the bottom FinFET, a top channel portion, associated with the top FinFET, and a channel isolator between the bottom channel portion and the top channel portion. A lower gate includes a vertical portion that is upon a sidewall of the bottom channel portion. An isolation layer may be formed upon the lower gate if it is desired for the top FinFET fin and the bottom FinFET fin to not share a gate. An upper gate is upon the top channel portion and is further upon the isolation layer, if present, or is upon the lower gate.

Abstract: A channel fin extends vertically above a bottom source/drain region, a protective liner is positioned along opposite sidewalls of the bottom source/drain region. The bottom source/drain region is positioned above a semiconductor layer in contact with a first portion of an inner spacer. A first metal layer is positioned between the first portion of the inner spacer and a second portion of the inner spacer, the first portion of the inner spacer partially covers a top surface of the first metal layer and the second portion of the inner spacer substantially covers a bottom surface of the first metal layer for providing a buried power rail. A shallow trench isolation region is positioned above an exposed portion of the first metal layer, the shallow trench isolation region is adjacent to the first portion of the inner spacer, the semiconductor layer, and the bottom source/drain region.

Abstract: Systems and methods for vanadium battery state-of-charge balance are disclosed. An example system includes a state-of-charge detection module, a state detection module, a control module and a plurality of vanadium battery modules in series. Each vanadium battery module includes positive and negative electrode electrolyte tanks, and a balance pipeline with a controllable switch between the positive and negative electrode electrolyte tanks of any two vanadium battery modules. The state-of-charge detection module detects and outputs the state-of-charge value of each vanadium battery module. The state detection module detects and outputs the charge and discharge states of the vanadium battery modules.

Abstract: A method of forming a semiconductor structure includes forming a first array of mandrels on a hardmask layer disposed on an uppermost surface of a semiconductor substrate. First sidewall image transfer spacers are formed on opposing longitudinal sidewalls of each mandrel in the first array of mandrels. A second array of mandrels is formed on the hardmask layer. Each mandrel in the second array of mandrels is laterally separated from each mandrel in the first array of mandrels by the first sidewall image transfer spacers. Second sidewall image transfer spacers are formed on opposing transversal sidewalls of the first array of mandrels and the second array of mandrels. Portions of the second sidewall image transfer spacers are selectively removed to define a crosslink fin pattern to be transferred to the semiconductor substrate.

Abstract: Embodiments herein include semiconductor structures with an active channel stack having an upper field-effect transistor (FET) and a lower FET vertically stacked below the upper FET The semiconductor structure may also include a dummy stub adjacent to the active channel stack, a lower source/drain (S/D) connected to the active channel stack and laterally extended over the dummy stub, and an upper S/D connected to the active channel stack above the lower S/D.

Abstract: Semiconductor devices and methods of forming the same include forming a first stack of nanosheets in a first region, the first stack of nanosheets including upper first nanosheets and lower first nanosheets. A second stack of nanosheets is formed in a second region, the second stack of nanosheets including upper second nanosheets and lower second nanosheets. A lower gate cut structure is formed between the lower first nanosheets and the lower second nanosheets. A gate stack is formed on the first and second stack of nanosheets after forming the lower gate cut structure. An upper gate cut structure is formed after forming the gate stack.

Abstract: A FET channel comprises a stack of silicon nanosheets. The silicon nanosheets are oriented parallel to a planar portion of the FET in which the FET channel is formed. The FET channel also comprises a vertical blocker fin. The vertical blocker fin is attached to at least one nanosheet in the stack of nanosheets.

Abstract: Monolithically stacked VTFET devices having source/drain contacts with increased contact area and dielectric isolation are provided. In one aspect, a stacked VTFET device includes: at least a bottom VTFET below a top VTFET, wherein the bottom VTFET and the top VTFET each includes source/drain regions interconnected by a vertical fin channel, and a gate stack alongside the vertical fin channel; and source/drain contacts to the source/drain regions, wherein at least one of the source/drain contacts is in direct contact with more than one surface of a given one of the source/drain regions. A stacked VTFET device having at least a bottom VTFET1 below a top VTFET1, and a bottom VTFET2 below a top VTFET2, and a method of forming a stacked VTFET device are also provided.

Abstract: Stacked field effect transistors are provided such having a first power rail; a second power rail; a first Field Effect Transistor (FET) having a first gate connected to the first power rail; a second FET having a second gate connected to the second power rail; and an insulator separating the first FET from the second FET, wherein the first power rail, the second power rail, the first FET, and the second FET are aligned on a shared axis, and wherein the first power rail and the second power rail are located on opposite sides of the device.

Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having defect free channels. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating first sacrificial layers and second sacrificial layers. One layer of the first sacrificial layers has a greater thickness than the remaining first sacrificial layers. The first sacrificial layers are removed and semiconductor layers are formed on surfaces of the second sacrificial layers. The semiconductor layers include a first set and a second set of semiconductor layers. The second sacrificial layers are removed and an isolation dielectric is formed between the first set and the second set of semiconductor layers.