Patents by Inventor Chen Zhang

Chen Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Work function metal patterning for nanosheet CFETs
    Patent number: 11798851
    Abstract: Semiconductor devices, and methods of forming the same, include forming a stack of channel layers, including an upper device region and a lower device region. The upper device region is separated from the lower device region by a dielectric spacer layer. A first work function metal layer is formed on the channel layers in the lower device region. A height of the first work function metal layer does not rise above the dielectric spacer layer. A second work function metal layer is formed on the channel layers in the upper device region.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: October 24, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruilong Xie, Chen Zhang, Kangguo Cheng, Juntao Li
  • AUTONOMOUS LANE MERGING SYSTEM AND METHOD
    Publication number: 20230322267
    Abstract: A computer-implemented method of performing an autonomous lane merging of a vehicle. The method includes: identifying one or more objects in a plurality of lanes in the vicinity of the vehicle; identifying one or more gaps among the one or more objects; determining a mode of the vehicle; determining a terminal state of a planned trajectory of the vehicle based on the identified objects, gaps, and the mode of the vehicle; performing a sanity check based on the terminal state of the planned trajectory; generating the planned trajectory of the vehicle if the sanity check passes; providing the planned trajectory to a controller of the vehicle to autonomously move the vehicle according to the planned trajectory.
    Type: Application
    Filed: April 12, 2022
    Publication date: October 12, 2023
    Inventors: Aohan Mei, Chen Zhang, Fan Wang
  • 980 MPA-GRADE FULL-BAINITE ULTRA-HIGH HOLE EXPANSION STEEL AND MANUFACTURING METHOD THEREFOR
    Publication number: 20230323502
    Abstract: A 980 MPa-grade full-bainite ultra-high hole expansion steel and a manufacturing method therefor. The hole expansion steel has the following chemical compositions in percentage by weight: 0.05-0.10% of C, Si?2.0%, 1.0-2.0% of Mn, P?0.02%, S?0.003%, 0.02-0.08% of Al, N?0.004%, 0.1-0.5% of Mo, 0.01-0.05% of Ti, O?0.0030%, the remainder being Fe, and other inevitable impurities. The ultra-high hole expansion steel in the present invention has yield strength ?800 MPa, tensile strength ?980 MPa, and a hole expansion rate up to 60% or more, and can be applied in the parts of chassis components such as a control arm and an auxiliary frame, which require high strength thinning and complex forming, of passenger vehicles.
    Type: Application
    Filed: August 30, 2021
    Publication date: October 12, 2023
    Applicant: BAOSHAN IRON & STEEL CO., LTD.
    Inventors: Huanrong WANG, Feng YANG, Chen ZHANG, Ana YANG, Yaping NI
  • 780 MPA-GRADE ULTRA-HIGH REAMING STEEL HAVING HIGH SURFACE QUALITY AND HIGH PERFORMANCE STABILITY, AND MANUFACTURING METHOD THEREFOR
    Publication number: 20230323500
    Abstract: A 780 MPa-grade ultra-high reaming steel having high surface quality and high performance stability, and a manufacturing method therefor. The ultra-high reaming steel comprises the following components in percentage by weight: 0.03-0.08% of C, Si?0.2%, 0.5-2.0% of Mn, P?0.02%, S?0.003%, 0.01-0.08% of Al, N?0.004%, 0.05-0.20% of Ti, 0.1-0.5% of Mo, Mg?0.005%, O?0.0030%, and the remainder being Fe and other inevitable impurities.
    Type: Application
    Filed: August 30, 2021
    Publication date: October 12, 2023
    Applicant: BAOSHAN IRON & STEEL CO., LTD.
    Inventors: Huanrong WANG, Feng YANG, Chen ZHANG, Ana YANG, Mingzhou BAI, Yaping NI, Ming WANG
  • STACKED FET SIDEWALL STRAP CONNECTIONS BETWEEN GATES
    Publication number: 20230317727
    Abstract: A set of stacked transistors, system, and method to connect the gates of stacked field-effect transistors through sidewall straps. The set of stacked transistors may include a first transistor including a first gate. The set of stacked transistors may also include a second transistor including a second gate, where the second transistor is above the first transistor. The set of stacked transistors may also include a dielectric preventing direct contact between the first gate and the second gate. The set of stacked transistors may also include a first sidewall strap proximately connected to the first gate and the second gate, where the first sidewall strap connects the first transistor and the second transistor.
    Type: Application
    Filed: March 29, 2022
    Publication date: October 5, 2023
    Inventors: Chen Zhang, Julien Frougier, Ruilong Xie, Heng Wu
  • HIGH-STRENGTH LOW-CARBON MARTENSITIC HIGH HOLE EXPANSION STEEL AND MANUFACTURING METHOD THEREFOR
    Publication number: 20230313332
    Abstract: A low-carbon martensitic high hole expansion steel with a tensile strength above 980 MPa, and a manufacturing method therefor, the weight percentage of the chemical components thereof being: C 0.03-0.10%, Si 0.5-2.0%, Mn 1.0-2.0%, P?0.02%, S?0.003%, Al 0.02-0.08%, N?0.004%, Mo 0.1-0.5%, Ti 0.01-0.05%, and O?0.0030%, and the remainder being Fe and other inevitable impurities. The high hole expansion steel of the present invention has a yield strength of ?800 MPa and tensile strength of ?980 MPa, a lateral extension rate A50?8%, and a hole expansion ratio of ?30%, passes cold bending performance tests (d?4a, 180°), and can be used for passenger car chassis parts that require high strength and thinning such as control arms and sub-frames.
    Type: Application
    Filed: August 30, 2021
    Publication date: October 5, 2023
    Applicant: BAOSHAN IRON & STEEL CO., LTD.
    Inventors: Huanrong WANG, Feng YANG, Chen ZHANG, Ana YANG, Yaping NI, Ming WANG, Mingzhou BAI
  • 980 MPA-GRADE BAINITE HIGH HOLE EXPANSION STEEL AND MANUFACTURING METHOD THEREFOR
    Publication number: 20230313333
    Abstract: Disclosed are a 980 MPa-grade bainite high hole expansion steel and a manufacturing method therefor. The steel contains the following chemical components in percentages by weight: 0.05-0.10% of C, 0.5-2.0% of Si, 1.0-2.0% of Mn, P?0.02%, S?0.003%, 0.02-0.08% of Al, N?0.004%, Mo?0.1%, 0.01-0.05% of Ti, Cr?0.5%, B?0.002%, O?0.0030%, and the balance of Fe and other inevitable impurities. The high hole expansion steel of the present invention has a yield strength of ?800 MPa and a tensile strength of ?980 MPa, has a good elongation rate (the transverse A50 being ?11%) and hole expansion performance (the hole expansion ratio being ?40%), and can be applied to a position on a chassis part of a passenger car, such as a control arm and a vice frame, where high strength and thinning are required.
    Type: Application
    Filed: August 30, 2021
    Publication date: October 5, 2023
    Applicant: BAOSHAN IRON & STEEL CO., LTD.
    Inventors: Huanrong WANG, Feng YANG, Chen ZHANG, Ana YANG
  • Hybrid complementary field effect transistor device
    Patent number: 11777034
    Abstract: A stacked transistor device is provided. The stacked transistor device includes a nanosheet transistor device on a substrate; and a fin field effect transistor device over the nanosheet transistor device to form the stacked transistor device, wherein the fin field effect transistor device is configured to have a current flow through the fin field effect transistor device perpendicular to a current flow through the nanosheet transistor device.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: October 3, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruilong Xie, Chen Zhang, Jingyun Zhang, Junli Wang, Pietro Montanini
  • EMBEDDED MAGNETORESISTIVE RANDOM ACCESS MEMORY
    Publication number: 20230309320
    Abstract: Embodiments are disclosed for a system. The system includes a semiconductor structure. The semiconductor structure includes a wafer, multiple transistors, and a magnetoresistive random access memory (MRAM) cell disposed on the backside of the wafer. The transistors are disposed on a front end of line (FEOL) of the wafer. The MRAM cell is connected to a source-drain of the transistors by a contact disposed on the backside of the wafer. The transistors are in direct electrical contact with the MRAM cell by at least one contact.
    Type: Application
    Filed: March 23, 2022
    Publication date: September 28, 2023
    Inventors: Heng Wu, Ruilong Xie, Julien Frougier, Min Gyu Sung, Chen Zhang
  • STACKED DEVICE WITH BURIED INTERCONNECT
    Publication number: 20230307296
    Abstract: A stacked field-effect transistors (FETs) layout and a method for fabrication are provided. The stacked FETs include a buried interconnect within the stacked devices which provides power to buried components without requiring a wired connection from a top of the stacked FET to the buried components. The buried interconnect allows for efficient scaling of the stacked devices without extraneous wiring from a top of the device to each epitaxial region/device within the overall device.
    Type: Application
    Filed: March 23, 2022
    Publication date: September 28, 2023
    Inventors: Ruilong XIE, Chen ZHANG, Heng WU, Julien FROUGIER, Alexander REZNICEK
  • CODE CHECKING METHOD AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM DEVICE
    Publication number: 20230305821
    Abstract: A code checking method includes: causing a compiler to generate a map file and a low-level code file(s) according to a high-level code file(s); obtaining target function information from the map file; finding a target code file from the low-level code file(s); obtaining a first return command of a target function name of the target function information from the target code file; traversing the low-level code file(s) to obtain each calling module name and a second return command of each calling function name; obtaining a second storage area of each calling module name from the map file; and generating a check failure result when calling of a target function name by each calling function name is not complied with a bank-switching compile form according to a first storage area of the target function information, the first return command, each second storage area, and each second return command.
    Type: Application
    Filed: August 10, 2022
    Publication date: September 28, 2023
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yong-Bo Cai, Jun-Chen Zhang, Ming-Rui Li
  • 980 MPA-GRADE ULTRA-LOW-CARBON MARTENSITE AND RETAINED AUSTENITE ULTRA-HIGH HOLE EXPANSION STEEL AND MANUFACTURING METHOD THEREFOR
    Publication number: 20230304121
    Abstract: A 980 MPa-grade ultra-low-carbon martensite and retained austenite ultra-high hole expansion steel and a manufacturing method therefor. The hole expansion steel comprises the following chemical components in percentage by weight: C 0.03%-0.06%, Si 0.8%-2.0%, Mn 1.0%-2.0%, P?0.02%, S?0.003%, Al 0.02%-0.08%, N?0.004%, Mo 0.1%-0.5%, Ti 0.01%-0.05%, and O?0.0030%. The high hole expansion steel of the present invention has the yield strength ?800 MPa, the tensile strength ?980 MPa, the elongation rate (horizontal A50?10%), the cold bending property (d?4a, 180°), and the hole expansion ratio ?80%, and can be applied to a chassis part of a passenger vehicle such as a control arm, an auxiliary frame and other parts that require high-strength thinning.
    Type: Application
    Filed: August 30, 2021
    Publication date: September 28, 2023
    Applicant: BAOSHAN IRON & STEEL CO., LTD.
    Inventors: Huanrong WANG, Chen ZHANG, Feng YANG, Ana YANG
  • Hybrid complementary metal-oxide semiconductor field effect transistor nanosheet device
    Patent number: 11769796
    Abstract: A semiconductor device formed by forming a stack of alternating horizontal nanosheet layers, recessing the stack for an n-type field effect transistor (nFET), growing crystalline semiconductor adjacent to the stack, forming vertical nanosheets from the crystalline semiconductor, forming inner spacers between the vertical nanosheets, and forming a high-k metal gate structure around the horizontal nanosheets and the vertical nanosheets.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: September 26, 2023
    Assignee: International Business Machines Corporation
    Inventors: Chen Zhang, Ruilong Xie, Tenko Yamashita
  • STACKED NANOSHEET TRANSISTOR WITH DEFECT FREE CHANNEL
    Publication number: 20230299176
    Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having defect free channels. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating first sacrificial layers and second sacrificial layers. One layer of the first sacrificial layers has a greater thickness than the remaining first sacrificial layers. The first sacrificial layers are removed and semiconductor layers are formed on surfaces of the second sacrificial layers. The semiconductor layers include a first set and a second set of semiconductor layers. The second sacrificial layers are removed and an isolation dielectric is formed between the first set and the second set of semiconductor layers.
    Type: Application
    Filed: May 26, 2023
    Publication date: September 21, 2023
    Inventors: Lan Yu, Kangguo Cheng, Heng Wu, Chen Zhang
  • BACK-END-OF-LINE VERTICAL-TRANSPORT TRANSISTOR
    Publication number: 20230299205
    Abstract: A semiconductor structure including a bottom source drain region arranged above front-end-of-line circuitry, a gate region disposed above and insulated from the bottom source drain region, a top source drain region disposed above and insulated from the gate region, and a channel region adjacent to the gate region and extending vertically from a top surface of the bottom source drain region to a bottom surface of the top source drain region.
    Type: Application
    Filed: March 18, 2022
    Publication date: September 21, 2023
    Inventors: Heng Wu, Julien Frougier, Ruilong Xie, Chen Zhang
  • Fabric-covered electronic device with touch sensor
    Patent number: 11762512
    Abstract: An electronic device such as a speaker device may have a curved housing characterized by a vertical longitudinal axis. A layer of fabric may cover the curved housing. A touch sensor may be used to detect touch input on the layer of fabric. The touch sensor may include capacitive touch sensor electrodes including drive lines and sense lines. In some arrangements, the touch sensor is formed from conductive strands in the layer of fabric. In other arrangements, the touch sensor is formed from conductive traces on a substrate. The substrate may be formed from portions of the curved housing or may be formed from a layer that is separate from the housing. Light-emitting components and/or fabric with different visual characteristics may be used to mark where the touch-sensitive regions of the fabric are located. The touch-sensitive regions may be shaped as media control symbols.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: September 19, 2023
    Assignee: Apple Inc.
    Inventors: Zhengyu Li, Elvis M. Kibiti, Ming Gao, Qiliang Xu, Chen Zhang
  • Vertical field-effect transistor with dielectric fin extension
    Patent number: 11764259
    Abstract: A vertical field-effect transistor includes a substrate comprising a semiconductor material; a first set of fins formed from the semiconductor material and extending vertically with respect to the substrate; and a second set of fins extending vertically with respect to the substrate, wherein ones of the second set of fins abut ones of the first set of fins. The second set of fins comprises a dielectric material.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: September 19, 2023
    Assignee: International Business Machines Corporation
    Inventors: Chen Zhang, Tenko Yamashita, Xin Miao, Wenyu Xu, Kangguo Cheng
  • VTFET with buried power rails
    Patent number: 11764298
    Abstract: A semiconductor device is provided. The semiconductor device includes a buried power rail, a buried oxide (BOX) layer formed on the buried power rail, a plurality of channel fins formed on the BOX layer, a bottom epitaxial layer formed on the BOX layer and between the channel fins such that the BOX layer is between the buried power rail and the bottom epitaxial layer, a gate stack formed over the bottom epitaxial layer and contacting the channel fins, the gate stack including a work function metal (WFM) layer and a high-? layer, and a top epitaxial layer formed on the gate stack. In the semiconductor device, between two adjacent ones of the channel fins the BOX layer has an opening so that the bottom epitaxial layer is electrically connected to the buried power rail.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: September 19, 2023
    Assignee: International Business Machines Corporation
    Inventors: Chen Zhang, Ruilong Xie, Heng Wu, Junli Wang, Brent Anderson
  • Neural network compression based on bank-balanced sparsity
    Patent number: 11763156
    Abstract: In embodiments of the present disclosure, there is provided an approach for neural network model compression based on bank-balanced sparsity. In embodiments of the present disclosure, a set of weight parameters, such as a weight matrix, in a neural network is divided into a plurality of equal-sized banks in terms of number of elements, and then all of the equal-sized banks are pruned at the same sparsity level. In this way, each pruned bank will have the same number of non-zero elements, which is suitable for hardware speedup. Moreover, since each bank is pruned independently in a fine granularity, the model accuracy can be ensured. Thus, according to embodiments of the present disclosure, the neural network compression method based on bank-balanced sparsity can achieve both high model accuracy and high hardware speedup.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: September 19, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Chen Zhang, Yunxin Liu
  • Moon-shaped bottom spacer for vertical transport field effect transistor (VTFET) devices
    Patent number: 11757036
    Abstract: A uniform moon-shaped bottom spacer for a VTFET device is provided utilizing a replacement bottom spacer that is epitaxially grown above a bottom source/drain region. After filling a trench that is formed into a substrate with a dielectric fill material that also covers the replacement bottom spacer, the replacement bottom spacer is accessed, removed and then replaced with a moon-shaped bottom spacer.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: September 12, 2023
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Chen Zhang, Julien Frougier, Alexander Reznicek, Shogo Mochizuki