Patents by Inventor Chieh Hsieh

Chieh Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Packaging structures and methods with a metal pillar
    Patent number: 9508666
    Abstract: A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: November 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Shang-Yun Hou, Kuo-Ching Hsu, Cheng-Chieh Hsieh, Ying-Ching Shih, Po-Hao Tsai, Cheng-Lin Huang, Jing-Cheng Lin
  • Goal-oriented numerical control automatic tuning system and method
    Patent number: 9501053
    Abstract: A goal-oriented numerical control automatic tuning system is used for a numerical controller of a machine tool to automatically tune the machine tool. The system includes a goal-oriented input module for receiving external goal values; a machining test path selecting module for receiving an external machining path; and an automatic machine-tuning equation module including a control equation with a predetermined equation coefficient for receiving the goal values and the machining path from the goal-oriented input module and the machining test path selecting module, respectively, such that an appropriate control parameter can be obtained by calculating the control equation based on the goal values and the machining path, and then this control parameter passed to a numerical controller in order to control actuation of the machine tool.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: November 22, 2016
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chien-Yi Lee, Hung-Chieh Hsieh, Cheng-Yu Chen, Hao-Wei Nien, Yi-Ying Lin
  • INTEGRATED CIRCUIT WITH WELL AND SUBSTRATE CONTACTS
    Publication number: 20160336343
    Abstract: An integrated circuit comprises standard cells arranged in rows and columns. The integrated circuit also comprises tap cells arranged in rows and columns. The tap cells each comprise a substrate having a first dopant type and a thickness from a first surface of the substrate to a second surface of the substrate. The integrated circuit further comprises a well region in the substrate having a second dopant type different from the first dopant type and a depth from the first surface of the substrate less than the thickness of the substrate. The integrated circuit additionally comprises a first quantity of rows of tap cells and a second quantity of rows of tap cells less than the first quantity. Each row of the first quantity of rows of tap cells comprises at least one well contact, and each row of tap cells of the second quantity of tap cells comprises at least one substrate contact.
    Type: Application
    Filed: October 6, 2015
    Publication date: November 17, 2016
    Inventors: Ming-Zhang KUO, Ho-Chieh HSIEH, Hui-Zhong ZHUANG, Kuo-Feng TSENG, Lee-Chung LU, Cheng-Chung LIN, Sang Hoo DHONG
  • Scan cell assignment
    Patent number: 9495495
    Abstract: One or more systems and methods for scan cell assignment for a design layout of a semiconductor arrangement are provided. The design layout is evaluated to identify a set of sequential cells, such as flip flops connected to circuitry by data paths. Sequential cells within the set of sequential cells are assigned to either a scan cell assignment or a non-scan cell assignment based upon a control path criterion, a register bank criterion, a pipeline depth criterion, a sequential loop criterion, or other criteria to create a cell assignment list. Scan paths are connected to sequential cells assigned to the scan cell assignment so that test patterns can be sent to and received from such sequential cells during testing of the semiconductor arrangement for defects. Power, performance, and area utilization are improved because at least some sequential cells are assigned to the non-scan cell assignment.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: November 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Cheng-Chung Lin, Ming-Zhang Kuo, Sang Hoo Dhong, Ho-Chieh Hsieh, Kuo Feng Tseng
  • Pillar design for conductive bump
    Patent number: 9496235
    Abstract: A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: November 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chieh Hsieh, Cheng-Lin Huang, Po-Hao Tsai, Shang-Yun Hou, Jing-Cheng Lin, Shin-Puu Jeng
  • FAN-OUT STACKED SYSTEM IN PACKAGE (SIP) HAVING DUMMY DIES AND METHODS OF MAKING THE SAME
    Publication number: 20160322330
    Abstract: An embodiment package includes a first fan-out tier, fan-out redistribution layers (RDLs) over the first fan-out tier, and a second fan-out tier over the fan-out RDLs. The first fan-out tier includes one or more first device dies and a first molding compound extending along sidewalls of the one or more first device dies. The second fan-out tier includes one or more second device dies bonded to fan-out RDLs, a dummy die bonded to the fan-out RDLs, and a second molding compound extending along sidewalls of the one or more second device dies and the dummy die. The fan-out RDLs electrically connects the one or more first device dies to the one or more second device dies, and the dummy die is substantially free of any active devices.
    Type: Application
    Filed: April 30, 2015
    Publication date: November 3, 2016
    Inventors: Tsung-Shu Lin, Hsien-Wei Chen, Cheng-Chieh Hsieh, Chang-Chia Huang
  • Reinforcement Structure and Method for Controlling Warpage of Chip Mounted on Substrate
    Publication number: 20160315057
    Abstract: A semiconductor device comprises a substrate, a die mounted on the substrate, a reinforcement plate bonded to the die, and an adhesive layer coupling the reinforcement plate to the die.
    Type: Application
    Filed: July 5, 2016
    Publication date: October 27, 2016
    Inventors: Chen-Hua Yu, Shang-Yun Hou, Cheng-Chieh Hsieh, Tsung-Shu Lin
  • Semiconductor package for thermal dissipation
    Patent number: 9449947
    Abstract: A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: September 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Der-Chyang Yeh, Hsien-Wei Chen, Cheng-Chieh Hsieh, Ming-Yen Chiu
  • Chip packages and methods of manufacturing the same
    Patent number: 9443806
    Abstract: Chip packages and methods of manufacture thereof are disclosed. In some embodiments, a chip package may include: a chip having a contact pad disposed at a first side of the chip; a passivation layer over the first side of the chip, the passivation layer having an opening disposed over the contact pad; a polymer layer over the passivation layer, the polymer layer having an edge disposed over the contact pad; a conductive structure formed atop the contact pad, the conductive structure filling the opening of the passivation layer and covering the edge of the polymer layer; and a frontside redistribution layer (RDL) disposed over the conductive structure, the frontside RDL having a first portion electrically connected to the conductive structure and a second portion electrically connected to the first portion and extending laterally away from the first portion and the conductive structure.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: September 13, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Cheng-Chieh Hsieh, Tsung-Shu Lin, Chen-Hua Yu
  • Thermal Structure for Integrated Circuit Package
    Publication number: 20160254211
    Abstract: One or more heat pipes are utilized along with a substrate in order to provide heat dissipation through the substrate for heat that can build up at an interface between the substrate and one or more semiconductor chips in a package. In an embodiment the heat pipe may be positioned on a side of the substrate opposite the semiconductor chip and through-substrate vias may be utilized to dissipate heat through the substrate. In an alternative embodiment, the heat pipe may be positioned on a same side of the substrate as the semiconductor chip and may be thermally connected to the one or more semiconductor chips.
    Type: Application
    Filed: May 9, 2016
    Publication date: September 1, 2016
    Inventors: Cheng-Chieh Hsieh, Shin-Puu Jeng, Shang-Yun Hou, Way Lee Cheng
  • Image Sensor Device and Method
    Publication number: 20160233347
    Abstract: A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration.
    Type: Application
    Filed: April 18, 2016
    Publication date: August 11, 2016
    Inventors: Kuo-Chin Huang, Tzu-Jui Wang, Szu-Ying Chen, Dun-Nian Yaung, Jen-Cheng Liu, Bruce C.S. Chou, Jung-Kuo Tu, Cheng-Chieh Hsieh
  • Methods for forming silicon-based hermetic thermal solutions
    Patent number: 9391000
    Abstract: A method includes forming a first oxide layer on a surface of an integrated heat spreader, and forming a second oxide layer on top surfaces of fins, wherein the fins are parts of a heat sink. The integrated heat spreader is bonded to the heat sink through the bonding of the first oxide layer to the second oxide layer.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: July 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chieh Hsieh, Jing-Cheng Lin
  • Reinforcement structure and method for controlling warpage of chip mounted on substrate
    Patent number: 9385091
    Abstract: A semiconductor device comprises a substrate, a die mounted on the substrate, a reinforcement plate bonded to the die, and an adhesive layer coupling the reinforcement plate to the die.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: July 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shang-Yun Hou, Cheng-Chieh Hsieh, Tsung-Shu Lin
  • Apparatus and method for reducing dark current in image sensors
    Patent number: 9379275
    Abstract: A method for reducing dark current in image sensors comprises providing a backside illuminated image sensor wafer, depositing a first passivation layer on a backside of the backside illuminated image sensor wafer, depositing a plasma enhanced passivation layer on the first passivation layer and depositing a second passivation layer on the plasma enhanced passivation layer.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: June 28, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Miao-Cheng Liao, Jinn-Kwei Liang, Wen-Chieh Hsieh, Shiu-Ko JangJian, Hsiang Hsiang Ko, Ying-Lang Wang
  • Thermal structure for integrated circuit package
    Patent number: 9337123
    Abstract: One or more heat pipes are utilized along with a substrate in order to provide heat dissipation through the substrate for heat that can build up at an interface between the substrate and one or more semiconductor chips in a package. In an embodiment the heat pipe may be positioned on a side of the substrate opposite the semiconductor chip and through-substrate vias may be utilized to dissipate heat through the substrate. In an alternative embodiment, the heat pipe may be positioned on a same side of the substrate as the semiconductor chip and may be thermally connected to the one or more semiconductor chips.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: May 10, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chieh Hsieh, Way Lee Cheng, Shang-Yun Hou, Shin-Puu Jeng
  • Image sensor device and method
    Patent number: 9318528
    Abstract: A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: April 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chin Huang, Tzu-Jui Wang, Szu-Ying Chen, Dun-Nian Yaung, Jen-Cheng Liu, Bruce C. S. Chou, Jung-Kuo Tu, Cheng-Chieh Hsieh
  • Stereoscopic display panel, display panel and driving method thereof
    Patent number: 9313478
    Abstract: A stereoscopic display panel, a display panel and a driving method thereof are provided. A pixel array of the pixel array substrate includes a first scan line, a second scan line, a first data line, a first pixel electrode, a second pixel electrode, a first active device and a second active device. The first data line is electrically connected to the first pixel electrode disposed at the left side of the first data line through the first active device. The first data line is electrically connected to the second pixel electrode disposed at the right side of the first data line through the second active device. The first scan line electrically connected to the first active device and the second scan line electrically connected to the second active device are disposed at the same side of the first active device and the second active device.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: April 12, 2016
    Assignee: Au Optronics Corporation
    Inventors: Jen-Chieh Hsieh, Wei-Kai Huang
  • Updating Method and Electronic System thereof
    Publication number: 20160085539
    Abstract: An updating method for an electronic system with a plurality of hardware devices is disclosed. The updating method includes selecting one of the plurality of hardware devices as a first layer device; selecting at least one of the hardware devices as at least one second layer device; performing, by the first layer device, an updating process according to a software component; transmitting, by the first layer device, a first notification message; and accessing, by the at least one second layer device, the software component from the first layer device according to the first notification message and performing, by the at least one second layer device, the updating process according to the software component.
    Type: Application
    Filed: November 26, 2014
    Publication date: March 24, 2016
    Inventor: Jung-Chieh Hsieh
  • Memory circuit for pre-charging and write driving
    Patent number: 9286970
    Abstract: A memory includes a word line, a bit line and a complementary bit line. A memory cell has a data node coupled to the bit line and a complementary data node coupled to the complementary bit line. The word line controls access to the memory cell. A circuit is coupled to the bit line and the complementary bit line. The circuit is configured to pull up to a high voltage, pull down to a low voltage, or float the bit line and the complementary bit line based on a first timing of pre-charging and a second timing of write driving. The first timing and the second timing are synchronized.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: March 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Zhang Kuo, Cheng-Chung Lin, Ho-Chieh Hsieh, Kuo Feng Tseng, Sang Hoo Dhong
  • Integrated Circuit Packages and Methods of Forming Same
    Publication number: 20160071816
    Abstract: Integrated circuit packages and methods of forming the same are provided. One or more redistribution layers are formed on a carrier. First connectors are formed on a first side of the RDLs. Dies are bonded to the first side of the RDLs using the first connectors. An encapsulant is formed on the first side of the RDLs around the dies. The carrier is de-bonded from the overlaying structure and second connectors are formed on a second side of the RDLs. The resulting structure in diced to form individual packages.
    Type: Application
    Filed: September 5, 2014
    Publication date: March 10, 2016
    Inventors: Lin-Chih Huang, Hung-An Teng, Hsin-Yu Chen, Tsang-Jiuh Wu, Cheng-Chieh Hsieh