Abstract: Methods for optimizing utilization of workload-consumed resources for time-inflexible workloads are disclosed. By sorting workload-consumed resource profiles representing individual workloads in one system according to an order of standard deviation or descending volume, two workload-consumed resource profiles can be combined to check if combination criteria are fulfilled. If any combination satisfies the combination criteria, corresponding workloads can be combined to share the same resource from the system. Thus, optimizing utilization of the workload-consumed resource can be achieved.

Abstract: A stack type test interface board assembly is provided herein, which comprises: a space transform board having a narrow pitch transform board and a wide pitch transform board, a plurality of first connection nodes disposed on a side of the narrow pitch transform board to be electrically connected to a finished or semi-finished semiconductor product, a plurality of second connection nodes disposed on a side of the wide pitch transform board, and a printed circuit board where a side thereof is electrically connected to the plurality of the second connection nodes. The narrow pitch transform board and the wide pitch transform board are assembled in perpendicular stack into the space transform board. A pitch between each two of the plurality of the first connection nodes is smaller than a pitch between each two of the plurality of the second connection nodes.

Abstract: A semiconductor device comprises a substrate, a die mounted on the substrate, a reinforcement plate bonded to the die, and an adhesive layer coupling the reinforcement plate to the die.

Abstract: A system, method, and apparatus are provided for cytometry with dual laser beams. In one example, the method includes directing an incident light beam from a source to enter an optical waveplate; polarizing the incident light beam into a polarized light beam in response to the incident light beam entering through the optical waveplate; directing the polarized light beam to enter a birefringent crystal; separating the polarized light beam into an ordinary light beam and an extraordinary light beam in response to the polarized light beam entering the birefringent crystal; directing the ordinary light beam and the extraordinary light beam to enter a lens; focusing the ordinary light beam and the extraordinary light beam into dual light beams separated by a beam displacement; and coupling the dual light beams to form a sample region having substantially uniform light intensity to analyze moving particles in the particle analyzer.

Abstract: A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.

Abstract: A gas chromatography system can include a circulatory loop, a gas inlet positioned along the circulatory loop, a gas outlet positioned along the circulatory loop, a micro column positioned in line with the circulatory loop, and an in-line population sensor positioned in line with the circulatory loop. The in-line population sensor can be configured to detect changes in gas population. The gas inlet and gas outlet can be associated with a gas inlet valve and gas outlet valve, and configured to admit or withdraw gas from the circulatory loop, respectively. A gas sample can be circulated through the circulatory loop for at least one cycle, and a component of the gas sample can be detected using the in-line population sensor.

Abstract: One or more heat pipes are utilized along with a substrate in order to provide heat dissipation through the substrate for heat that can build up at an interface between the substrate and one or more semiconductor chips in a package. In an embodiment the heat pipe may be positioned on a side of the substrate opposite the semiconductor chip and through-substrate vias may be utilized to dissipate heat through the substrate. In an alternative embodiment, the heat pipe may be positioned on a same side of the substrate as the semiconductor chip and may be thermally connected to the one or more semiconductor chips.

Abstract: A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration.

Abstract: A semiconductor device with an anti-pad peeling structure is disclosed. The semiconductor device includes: a semiconductor substrate including a Through Substrate Via (TSV); a dielectric layer on the semiconductor substrate and including a plurality of recesses therein; and a pad above the semiconductor substrate to cover a portion of the dielectric layer and extend to the recesses; wherein the pad extends to the plurality of recesses, and a plurality of contact points are confined in the recesses between the pad and the conductive layer, and each of the contact points is at least partially excluded from a boundary of the TSV when being seen from a top-down perspective.

Abstract: A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.

Abstract: An integrated circuit comprises standard cells arranged in rows and columns. The integrated circuit also comprises tap cells arranged in rows and columns. The tap cells each comprise a substrate having a first dopant type and a thickness from a first surface of the substrate to a second surface of the substrate. The integrated circuit further comprises a well region in the substrate having a second dopant type different from the first dopant type and a depth from the first surface of the substrate less than the thickness of the substrate. The integrated circuit additionally comprises a first quantity of rows of tap cells and a second quantity of rows of tap cells less than the first quantity. Each row of the first quantity of rows of tap cells comprises at least one well contact, and each row of tap cells of the second quantity of tap cells comprises at least one substrate contact.

Abstract: Keep out zones (KOZ) are formed for a through silicon via (TSV). A device can be placed outside a first KOZ of a TSV determined by a first performance threshold so that a stress impact caused by the TSV to the device is less than a first performance threshold while the first KOZ contains only those points at which a stress impact caused by the TSV is larger than or equal to the first performance threshold. A second KOZ for the TSV can be similarly formed by a second performance threshold. A plurality of TSVs can be placed in a direction that the KOZ of the TSV has smallest radius to a center of the TSV, which may be in a crystal orientation [010] or [100]. A plurality of TSV stress plug can be formed at the boundary of the overall KOZ of the plurality of TSVs.

Abstract: A semiconductor device with an anti-pad peeling structure is disclosed. The semiconductor device includes: a semiconductor substrate including a Through Substrate Via (TSV); a dielectric layer on the semiconductor substrate and including a plurality of recesses therein; and a pad above the semiconductor substrate to cover a portion of the dielectric layer and extend to the recesses; wherein the pad extends to the plurality of recesses, and a plurality of contact points are confined in the recesses between the pad and the conductive layer, and each of the contact points is at least partially excluded from a boundary of the TSV when being seen from a top-down perspective.

Abstract: Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a cooling device for a semiconductor device includes a reservoir having a first plate and a second plate coupled to the first plate. A cavity is between the first plate and the second plate. A phase change material (PCM) is in the cavity. The cooling device is adapted to dissipate heat from a packaged semiconductor device.

Abstract: An embodiment package includes a first fan-out tier, fan-out redistribution layers (RDLs) over the first fan-out tier, and a second fan-out tier over the fan-out RDLs. The first fan-out tier includes one or more first device dies and a first molding compound extending along sidewalls of the one or more first device dies. The second fan-out tier includes one or more second device dies bonded to fan-out RDLs, a dummy die bonded to the fan-out RDLs, and a second molding compound extending along sidewalls of the one or more second device dies and the dummy die. The fan-out RDLs electrically connects the one or more first device dies to the one or more second device dies, and the dummy die is substantially free of any active devices.

Abstract: A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material.

Abstract: A method for fabricating a semiconductor device on a wafer includes: patterning a plurality of fins on the wafer; forming a shallow-trench isolation region to surround the plurality of fins; and etching the STI region to form the plurality of fins having a fin height such that the semiconductor device has a desired power consumption. The plurality of fins corresponds to a plurality of finFETs of the semiconductor device respectively.

Abstract: A method of fabricating a light pipe of an image sensing device including following steps is provided. A substrate is provided. The substrate includes a pixel region and a periphery region. A light sensing region has been formed in the substrate. The light sensing region is located in the pixel region. A dielectric layer is formed on the substrate. An interconnection structure and a light-blocking metal layer have been formed in the dielectric layer. The light-blocking metal layer is located over the interconnection structure, and the light-blocking metal layer has an opening exposing the light sensing region. A portion of the dielectric layer exposed by the opening is removed by using the light-blocking metal layer as a mask to form the light pipe in the dielectric layer.

Abstract: A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.

Abstract: Disclosed is a multilayer interposer with high bonding strength, which is used in wafer testing. The multilayer interposer with high bonding strength comprises a plurality of thin-film layer structures overlapping sequentially. One of the thin-film layer structures comprises at least one first conductive blind via. An interconnection layer electrically connected to the first conductive blind via is configured on the surface of the one of the thin-film layer structures, and the interconnection layer comprises at least one head portion. Another one of the thin-film layer structures comprises at least one second conductive blind via. The bottom of the second conductive blind via contacts both of the corresponding head portion and part of the surface of the one of the thin-film layer structures. Thereby, the bonding strength between layers can be dramatically increased, and the resistance to the thermal shock can be also increased.