Patents by Inventor Chieh Hsieh

Chieh Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Image Sensor Device and Method
    Publication number: 20160035771
    Abstract: A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration.
    Type: Application
    Filed: October 12, 2015
    Publication date: February 4, 2016
    Inventors: Kuo-Chin Huang, Tzu-Jui Wang, Szu-Ying Chen, Dun-Nian Yaung, Jen-Cheng Liu, Bruce C.S. Chou, Jung-Kuo Tu, Cheng-Chieh Hsieh
  • MEMORY CIRCUIT FOR PRE-CHARGING AND WRITE DRIVING
    Publication number: 20160012881
    Abstract: A memory includes a word line, a bit line and a complementary bit line. A memory cell has a data node coupled to the bit line and a complementary data node coupled to the complementary bit line. The word line controls access to the memory cell. A circuit is coupled to the bit line and the complementary bit line. The circuit is configured to pull up to a high voltage, pull down to a low voltage, or float the bit line and the complementary bit line based on a first timing of pre-charging and a second timing of write driving. The first timing and the second timing are synchronized.
    Type: Application
    Filed: July 8, 2014
    Publication date: January 14, 2016
    Inventors: Ming-Zhang Kuo, Cheng-Chung Lin, Ho-Chieh Hsieh, Kuo Feng Tseng, Sang Hoo Dhong
  • Semiconductor Package and Method
    Publication number: 20160005716
    Abstract: A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.
    Type: Application
    Filed: July 1, 2014
    Publication date: January 7, 2016
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Der-Chyang Yeh, Hsien-Wei Chen, Cheng-Chieh Hsieh, Ming-Yen Chiu
  • Three-dimensional printing apparatus
    Patent number: 9211676
    Abstract: A three-dimensional (3-D) printing apparatus includes a base, a printing head module and a control unit. The base includes a carrying surface and a guiding mechanism. The guiding mechanism extends along a long-axis direction of the base. The printing head module movably disposed on the guiding mechanism. The length of the base is greater than the length of the printing head module, such that the printing head module is suitable for moving relatively to the guiding mechanism. The control unit coupled to the base and the printing head module controls the printing head module to move relatively to the base according to extensional information of the digital 3-D model along the long-axis direction, such that the printing head module dispenses a material on the carrying surface to form a 3-D object when moving relatively to the base.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: December 15, 2015
    Assignees: XYZprinting, Inc., Kinpo Electronics, Inc., Cal-Comp Electronics & Communications Company Limited
    Inventor: Wen-Chieh Hsieh
  • Contact Pad for Semiconductor Device
    Publication number: 20150348877
    Abstract: A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.
    Type: Application
    Filed: September 2, 2014
    Publication date: December 3, 2015
    Inventors: Chang-Chia Huang, Tsung-Shu Lin, Cheng-Chieh Hsieh, Wei-Cheng Wu
  • CHIP PACKAGES AND METHODS OF MANUFACTURING THE SAME
    Publication number: 20150325536
    Abstract: Chip packages and methods of manufacture thereof are disclosed. In some embodiments, a chip package may include: a chip having a contact pad disposed at a first side of the chip; a passivation layer over the first side of the chip, the passivation layer having an opening disposed over the contact pad; a polymer layer over the passivation layer, the polymer layer having an edge disposed over the contact pad; a conductive structure formed atop the contact pad, the conductive structure filling the opening of the passivation layer and covering the edge of the polymer layer; and a frontside redistribution layer (RDL) disposed over the conductive structure, the frontside RDL having a first portion electrically connected to the conductive structure and a second portion electrically connected to the first portion and extending laterally away from the first portion and the conductive structure.
    Type: Application
    Filed: September 19, 2014
    Publication date: November 12, 2015
    Inventors: Shin-Puu Jeng, Cheng-Chieh Hsieh, Tsung-Shu Lin, Chen-Hua Yu
  • Image sensor device and method
    Patent number: 9159852
    Abstract: A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: October 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chin Huang, Tzu-Jui Wang, Szu-Ying Chen, Dun-Nian Yaung, Jen-Cheng Liu, Bruce C. S. Chou, Jung-Kuo Tu, Cheng-Chieh Hsieh
  • SCAN CELL ASSIGNMENT
    Publication number: 20150286760
    Abstract: One or more systems and methods for scan cell assignment for a design layout of a semiconductor arrangement are provided. The design layout is evaluated to identify a set of sequential cells, such as flip flops connected to circuitry by data paths. Sequential cells within the set of sequential cells are assigned to either a scan cell assignment or a non-scan cell assignment based upon a control path criterion, a register bank criterion, a pipeline depth criterion, a sequential loop criterion, or other criteria to create a cell assignment list. Scan paths are connected to sequential cells assigned to the scan cell assignment so that test patterns can be sent to and received from such sequential cells during testing of the semiconductor arrangement for defects. Power, performance, and area utilization are improved because at least some sequential cells are assigned to the non-scan cell assignment.
    Type: Application
    Filed: April 3, 2014
    Publication date: October 8, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Cheng-Chung Lin, Ming-Zhang Kuo, Sang Hoo Dhong, Ho-Chieh Hsieh, Kuo Feng Tseng
  • Through Silicon Via Keep Out Zone Formation Method and System
    Publication number: 20150270230
    Abstract: Keep out zones (KOZ) are formed for a through silicon via (TSV). A device can be placed outside a first KOZ of a TSV determined by a first performance threshold so that a stress impact caused by the TSV to the device is less than a first performance threshold while the first KOZ contains only those points at which a stress impact caused by the TSV is larger than or equal to the first performance threshold. A second KOZ for the TSV can be similarly formed by a second performance threshold. A plurality of TSVs can be placed in a direction that the KOZ of the TSV has smallest radius to a center of the TSV, which may be in a crystal orientation [010] or [100]. A plurality of TSV stress plug can be formed at the boundary of the overall KOZ of the plurality of TSVs.
    Type: Application
    Filed: June 8, 2015
    Publication date: September 24, 2015
    Inventors: Cheng-Chieh Hsieh, Hung-An Teng, Shang-Yun Hou, Shin-Puu Jeng
  • SCANNER
    Publication number: 20150172630
    Abstract: A scanner includes a rotary platform having a carrying surface, a support rack, an adjustment mechanism, a sensing device, and a control unit. The rotary platform is at one end of the support rack. The adjustment mechanism is at the other end of the support rack. The sensing device is arranged on the adjustment mechanism to generate a first or second sensing signal when the sensing device rotates to a first location. The control unit is coupled to the sensing device, the adjustment mechanism, and the rotary platform to rotate the rotary platform according to the first sensing signal, drive the sensing device to perform 3-D scanning on an object, or control the adjustment mechanism to drive the sensing device to rotate by a specific angle according to the second sensing signal, so that the sensing device faces the carrying surface to perform 2-D scanning on the object.
    Type: Application
    Filed: March 18, 2014
    Publication date: June 18, 2015
    Applicants: XYZprinting, Inc., Cal-Comp Electronics & Communications Company Limited, Kinpo Electronics, Inc.
    Inventor: Wen-Chieh Hsieh
  • THREE-DIMENSIONAL PRINTING APPARATUS
    Publication number: 20150158250
    Abstract: A three-dimensional (3-D) printing apparatus includes a base, a printing head module and a control unit. The base includes a carrying surface and a guiding mechanism. The guiding mechanism extends along a long-axis direction of the base. The printing head module movably disposed on the guiding mechanism. The length of the base is greater than the length of the printing head module, such that the printing head module is suitable for moving relatively to the guiding mechanism. The control unit coupled to the base and the printing head module controls the printing head module to move relatively to the base according to extensional information of the digital 3-D model along the long-axis direction, such that the printing head module dispenses a material on the carrying surface to form a 3-D object when moving relatively to the base.
    Type: Application
    Filed: January 29, 2014
    Publication date: June 11, 2015
    Applicants: XYZprinting, Inc., Cal-Comp Electronics & Communications Company Limited, Kinpo Electronics, Inc.
    Inventor: Wen-Chieh Hsieh
  • Through silicon via keep out zone formation method and system
    Patent number: 9054166
    Abstract: Keep out zones (KOZ) are formed for a through silicon via (TSV). A device can be placed outside a first KOZ of a TSV determined by a first performance threshold so that a stress impact caused by the TSV to the device is less than a first performance threshold while the first KOZ contains only those points at which a stress impact caused by the TSV is larger than or equal to the first performance threshold. A second KOZ for the TSV can be similarly formed by a second performance threshold. A plurality of TSVs can be placed in a direction that the KOZ of the TSV has smallest radius to a center of the TSV, which may be in a crystal orientation [010] or [100]. A plurality of TSV stress plug can be formed at the boundary of the overall KOZ of the plurality of TSVs.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: June 9, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chieh Hsieh, Hung-An Teng, Shang-Yun Hou, Shin-Puu Jeng
  • Integrated thermal solutions for packaging integrated circuits
    Patent number: 9034695
    Abstract: A method includes attaching a wafer on a carrier through an adhesive, and forming trenches in the carrier to convert the carrier into a heat sink. The heat sink, the carrier, and the adhesive are sawed into a plurality of packages.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chieh Hsieh, Shang-Yun Hou, Shin-Puu Jeng
  • Solar array with electrical transmission line communication
    Patent number: 8965596
    Abstract: A solar string includes first and second solar modules coupled to first and second filters by an electric transmission line. The second solar module includes a solar panel including a plurality of photovoltaic cells configured to convert photon energy to electrical energy. A processor is coupled to the solar panel and is in communication with the first solar module. The processor is configured to monitor an output of the solar panel and to transmit a status signal including an environmental condition of the second solar module to the first solar module by way of the electric transmission line. The first and second filters are configured to pass electrical power to a central inverter of a solar array in which the solar string is disposed and to prevent the status signal transmitted from the second solar module to the first solar module from being transmitted to the central inverter.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: February 24, 2015
    Assignee: TSMC Solar Ltd.
    Inventors: Szu-Han Li, Chih-Chieh Hsieh, Tong Hong Fu
  • Optical spectrum analyzer with continuously rotating tunable filter
    Patent number: 8953161
    Abstract: An optical spectrum analyzer is implemented with a detector combined with a tunable filter mounted on a stage capable of 360-degree rotation at a constant velocity. Because of the constant rate of angular change, different portions of the input spectrum are detected at each increment of time as a function of filter position, which can be easily measured with an encoder for synchronization purposes. The unidirectional motion of the mirror permits operation at very high speeds with great mechanical reliability. The same improvements may be obtained using a diffraction grating or a prism, in which case the detector or an intervening mirror may be rotated instead of the grating or prism.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: February 10, 2015
    Assignee: Optoplex Corporation
    Inventors: Yung-Chieh Hsieh, Chiayu Ai
  • Single-package dual optical-function device
    Patent number: 8929700
    Abstract: A four-fiber collimator is coupled to the optics of a single interleaver to produce the functionality of two co-packaged interleavers. Two fibers of the collimator are coupled to the core optics of a single interleaver to produce two pairs of output beams. The other two fibers of the collimators are coupled to receive the reflection output beams. The geometry of the optical fibers in the bundle is controlled to produce interleaver outputs with no offset. In another embodiment two fibers of the four-fiber collimator are coupled as inputs to and the other two fibers as outputs from a Fabry-Perot etalon. The geometry of the fibers and the focal length of the collimator are controlled to produce two outputs with peaks offset by a predetermined amount.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: January 6, 2015
    Assignee: Optoplex Corporation
    Inventor: Yung-Chieh Hsieh
  • Pillar Design for Conductive Bump
    Publication number: 20140361432
    Abstract: A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material.
    Type: Application
    Filed: August 22, 2014
    Publication date: December 11, 2014
    Inventors: Cheng-Chieh Hsieh, Cheng-Lin Huang, Po-Hao Tsai, Shang-Yun Hou, Jing-Cheng Lin, Shin-Puu Jeng
  • Connector design for packaging integrated circuits
    Patent number: 8901735
    Abstract: A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: December 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Ying Ching Shih, Po-Hao Tsai, Chin-Fu Kao, Cheng-Lin Huang, Cheng-Chieh Hsieh, Kuo-Ching Hsu, Jing-Cheng Lin, Shang-Yun Hou, Shin-Puu Jeng
  • Optical spectrum analyzer actuated by voice coil
    Patent number: 8885159
    Abstract: An optical spectrum analyzer includes a multilayer-coating filter for separating a wavelength in the spectrum of an incident input beam, a detector optically coupled to the filter, a voice-coil actuator for rotating the filter in oscillating motion to vary the wavelength received by the detector as a function of time, and an encoder for synchronizing the angular position of the filter with the wavelength received at the detector. The use of the voice-coil actuator makes it possible to achieve significantly greater speeds of operation with a significantly smaller device.
    Type: Grant
    Filed: May 12, 2012
    Date of Patent: November 11, 2014
    Assignee: Optoplex Corporation
    Inventor: Yung-Chieh Hsieh
  • 3D semiconductor package interposer with die cavity
    Patent number: 8865521
    Abstract: A 3D semiconductor package using an interposer is provided. In an embodiment, an interposer is provided having a first die electrically coupled to a first side of the interposer and a second die electrically coupled to a second side of the interposer. The interposer is electrically coupled to an underlying substrate, such as a packaging substrate, a high-density interconnect, a printed circuit board, or the like. The substrate has a cavity such that the second die is positioned within the cavity. The use of a cavity may allow smaller conductive bumps to be used, thereby allowing a higher number of conductive bumps to be used. A heat sink may be placed within the cavity to aid in the dissipation of the heat from the second die.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: October 21, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Kim Hong Chen, Shang-Yun Hou, Chao-Wen Shih, Cheng-Chieh Hsieh, Chen-Hua Yu