Patents by Inventor Chieh Hsieh

Chieh Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Image Sensor Device and Method
    Publication number: 20140264698
    Abstract: A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration.
    Type: Application
    Filed: June 27, 2013
    Publication date: September 18, 2014
    Inventors: Kuo-Chin Huang, Tzu-Jui Wang, Szu-Ying Chen, Dun-Nian Yaung, Jen-Cheng Liu, Bruce C.S. Chou, Jung-Kuo Tu, Cheng-Chieh Hsieh
  • PACKAGE DEVICE INCLUDING AN OPENING IN A FLEXIBLE SUBSTRATE AND METHODS OF FORMING THE SAME
    Publication number: 20140264803
    Abstract: Methods and apparatus are disclosed for forming ultra-thin packages for semiconductor devices on flexible substrates. A flexible substrate may comprise a plurality of insulating layers and redistribution layers. Openings of the flexible substrate may be formed at one side of the flexible substrate, two sides of the flexible substrate, or simply cut through the flexible substrate to divide the flexible substrate into two parts. Connectors may be placed within the opening of the flexible substrate and connected to redistribution layers of the flexible substrate. Dies can be attached to the connectors and electrically connected to the connectors and to the redistribution layers of the flexible substrate. Structure supports may be placed at another side of the flexible substrate on the surface or within an opening.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Inventors: Tsung-Shu Lin, Cheng-Chieh Hsieh, Hung-An Teng, Sao-Ling Chiu, Shang-Yun Hou
  • Package device including an opening in a flexible substrate and methods of forming the same
    Patent number: 8836094
    Abstract: Methods and apparatus are disclosed for forming ultra-thin packages for semiconductor devices on flexible substrates. A flexible substrate may comprise a plurality of insulating layers and redistribution layers. Openings of the flexible substrate may be formed at one side of the flexible substrate, two sides of the flexible substrate, or simply cut through the flexible substrate to divide the flexible substrate into two parts. Connectors may be placed within the opening of the flexible substrate and connected to redistribution layers of the flexible substrate. Dies can be attached to the connectors and electrically connected to the connectors and to the redistribution layers of the flexible substrate. Structure supports may be placed at another side of the flexible substrate on the surface or within an opening.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Shu Lin, Cheng-Chieh Hsieh, Hung-An Teng, Sao-Ling Chiu, Shang-Yun Hou
  • REINFORCEMENT STRUCTURE AND METHOD FOR CONTROLLING WARPAGE OF CHIP MOUNTED ON SUBSTRATE
    Publication number: 20140252591
    Abstract: A semiconductor device comprises a substrate, a die mounted on the substrate, a reinforcement plate bonded to the die, and an adhesive layer coupling the reinforcement plate to the die.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shang-Yun Hou, Cheng-Chieh Hsieh, Tsung-Shu Lin
  • Pillar design for conductive bump
    Patent number: 8816498
    Abstract: A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: August 26, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chieh Hsieh, Cheng-Lin Huang, Po-Hao Tsai, Shang-Yun Hou, Jing-Cheng Lin, Shin-Puu Jeng
  • LOW-DISPERSION STEP-PHASE INTERFEROMETER
    Publication number: 20140226164
    Abstract: Optical communication systems are sensitive to chromatic dispersion. An optical interleaver structure is provided that provides a significantly reduced dispersion, obtained by using at least one of a proper coating and a desired phase offset of each interfering cavity.
    Type: Application
    Filed: December 18, 2013
    Publication date: August 14, 2014
    Inventor: Yung-Chieh Hsieh
  • EFFICIENCY OF A DEEP GRATING
    Publication number: 20140211314
    Abstract: Several techniques are provided to reduce the spurious reflection generated at the exit surface of a transmission grating. In one embodiment the exit surface of the grating is not parallel with the entrance surface. In another embodiment, the first and second surfaces of the grating are parallel and a second substrate is attached to the second surface of the grating. The second substrate has an entrance surface and an exit surface having at least a wedge angle relative to the entrance surface. In another embodiment, a second substrate is fixedly connected to the second surface of a parallel plate grating, where the second substrate has an entrance surface and an exit surface. The exit surface is curved such that it will be about normal to a beam transmitted over a range of angels of incidence onto the grating region.
    Type: Application
    Filed: April 1, 2014
    Publication date: July 31, 2014
    Applicant: Optoplex Corporation
    Inventor: Yung-Chieh Hsieh
  • HIGH RESOLUTION FAST TUNABLE FILTER USING A TUNABLE COMB FILTER
    Publication number: 20140209795
    Abstract: High resolution fast tunable optical filters are described such that each filter includes a tunable single-peak narrow-bandwidth (SPNB) filter and a tunable etalon in tandem with the tunable SPNB filter, where the bandwidth of the tunable SPNB filter is less than the free spectral range (FSR) of the tunable etalon.
    Type: Application
    Filed: April 1, 2014
    Publication date: July 31, 2014
    Applicant: Optoplex Corporation
    Inventor: Yung-Chieh Hsieh
  • Thermal analysis of integrated circuit packages
    Patent number: 8782593
    Abstract: A method includes retrieving a first component information of a secured portion of a package, wherein the first component information is encrypted. The step of retrieving includes decrypting the first component information. A thermal resistance-network (R-network) is generated from the decrypted first component information. A temperature map of the package is generated using the thermal R-network and a second component information of an unsecured portion of the package, wherein the secured portion and the unsecured portion are bonded to each other.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: July 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Min Fu, Wan-Yu Lo, Meng-Fu You, Po-Hsiang Huang, Cheng-Chieh Hsieh
  • Super-Steep Step-Phase Interferometer
    Publication number: 20140176956
    Abstract: Step-phase interferometers are provided for use as optical interleavers/de-interleaver for optical communication. High data rates require a wide band-width to pass the high-speed modulated optical spectrum, and further require a wide stop-band to reject the signal from adjacent channels. The present interferometers provide a steep slope at the transition from the passband to the adjacent stop-band, thereby enlarging the width of both the pass-band and stop-band.
    Type: Application
    Filed: November 23, 2013
    Publication date: June 26, 2014
    Inventor: Yung-Chieh Hsieh
  • Connector Design for Packaging Integrated Circuits
    Publication number: 20140131864
    Abstract: A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.
    Type: Application
    Filed: January 22, 2014
    Publication date: May 15, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Ying Ching Shih, Po-Hao Tsai, Chin-Fu Kao, Cheng-Lin Huang, Cheng-Chieh Hsieh, Kuo-Ching Hsu, Jing-Cheng Lin, Shang-Yun Hou, Shin-Puu Jeng
  • GOAL-ORIENTED NUMERICAL CONTROL AUTOMATIC TUNING SYSTEM AND METHOD
    Publication number: 20140129024
    Abstract: A goal-oriented numerical control automatic tuning system is used for a numerical controller of a machine tool to automatically tune the machine tool. The system includes a goal-oriented input module for receiving external goal values; a machining test path selecting module for receiving an external machining path; and an automatic machine-tuning equation module including a control equation with a predetermined equation coefficient for receiving the goal values and the machining path from the goal-oriented input module and the machining test path selecting module, respectively, such that an appropriate control parameter can be obtained by calculating the control equation based on the goal values and the machining path, and then this control parameter passed to a numerical controller in order to control actuation of the machine tool.
    Type: Application
    Filed: May 17, 2013
    Publication date: May 8, 2014
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE-LON
    Inventors: Chien-Yi LEE, Hung-Chieh HSIEH, Cheng-Yu CHEN, Hao-Wei NIEN, Yi-Ying LIN
  • OPTICAL SPECTRUM ANALYZER WITH CONTINUOUSLY ROTATING TUNABLE FILTER
    Publication number: 20140125975
    Abstract: An optical spectrum analyzer is implemented with a detector combined with a tunable filter mounted on a stage capable of 360-degree rotation at a constant velocity. Because of the constant rate of angular change, different portions of the input spectrum are detected at each increment of time as a function of filter position, which can be easily measured with an encoder for synchronization purposes. The unidirectional motion of the mirror permits operation at very high speeds with great mechanical reliability. The same improvements may be obtained using a diffraction grating or a prism, in which case the detector or an intervening mirror may be rotated instead of the grating or prism.
    Type: Application
    Filed: November 5, 2012
    Publication date: May 8, 2014
    Applicant: OPTOPLEX CORPORATION
    Inventors: YUNG-CHIEH HSIEH, Chiayu AI
  • ILLUMINATION APPARATUS
    Publication number: 20140119029
    Abstract: An illumination apparatus includes a substrate, a reflective cup, an illumination unit and a lens structure. The reflective cup is placed on the substrate, and includes a plurality of first fasteners. The first fasteners are placed on the outer surface of the reflective cup. The illumination unit is mounted on the substrate within the reflective cup. The lens structure covers the reflective cup, and includes a plurality of second fasteners. The second fasteners can be removably engaged with the first fasteners, so that the lens structure can be fastened on the reflective cup.
    Type: Application
    Filed: August 30, 2013
    Publication date: May 1, 2014
    Applicant: Lextar Electronics Corporation
    Inventor: Cheng-Chieh HSIEH
  • Modified Michelson delay-line interferometer
    Patent number: 8705176
    Abstract: In an optical etalon with a fixed FSR determined by the cavity length, the time delay is adjusted by an etalon surface coating. The proper cavity length is chosen to achieve a desired FSR, and the coating is independently selected to obtain a desired time delay.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: April 22, 2014
    Assignee: Optoplex Corporation
    Inventor: Yung-Chieh Hsieh
  • Thermal Analysis of Integrated Circuit Packages
    Publication number: 20140089876
    Abstract: A method includes retrieving a first component information of a secured portion of a package, wherein the first component information is encrypted. The step of retrieving includes decrypting the first component information. A thermal resistance-network (R-network) is generated from the decrypted first component information. A temperature map of the package is generated using the thermal R-network and a second component information of an unsecured portion of the package, wherein the secured portion and the unsecured portion are bonded to each other.
    Type: Application
    Filed: September 25, 2012
    Publication date: March 27, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Min Fu, Wan-Yu Lo, Meng-Fu You, Po-Hsiang Huang, Cheng-Chieh Hsieh
  • FINE PITCH INTERPOSER STRUCTURE
    Publication number: 20140084955
    Abstract: A fine pitch interposer structure includes a Multi-core base substrate and a plurality of buildup laminates. A surface of each Multi-core base substrate has a first circuit layer, and a second circuit layer which is electrically connected to the first circuit layer. The buildup laminates are stacked on the surface of the Multi-core base substrate. Each buildup laminate includes a photosensitive dielectric layer, and a plurality of blind vias with a pre-determined interval therebetween which are correspondingly arranged on each of the plurality of vias formed on the photosensitive dielectric layer. The blind vias are electrically connected to the first circuit layer. At least one blind via of one buildup laminate is superimposed on another blind via of another buildup laminate.
    Type: Application
    Filed: March 15, 2013
    Publication date: March 27, 2014
    Applicant: CHUNGHWA PRECISION TEST TECH CO., LTD.
    Inventors: YUAN-CHIANG TENG, KAI-CHIEH HSIEH, WEN-TSUNG LEE
  • Connector design for packaging integrated circuits
    Patent number: 8664760
    Abstract: A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: March 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Shang-Yun Hou, Cheng-Chieh Hsieh, Kuo-Ching Hsu, Ying-Ching Shih, Po-Hao Tsai, Chin-Fu Kao, Cheng-Lin Huang, Jing-Cheng Lin
  • STEREOSCOPIC DISPLAY PANEL, DISPLAY PANEL AND DRIVING METHOD THEREOF
    Publication number: 20140049619
    Abstract: A stereoscopic display panel, a display panel and a driving method thereof are provided. A pixel array of the pixel array substrate includes a first scan line, a second scan line, a first data line, a first pixel electrode, a second pixel electrode, a first active device and a second active device. The first data line is electrically connected to the first pixel electrode disposed at the left side of the first data line through the first active device. The first data line is electrically connected to the second pixel electrode disposed at the right side of the first data line through the second active device. The first scan line electrically connected to the first active device and the second scan line electrically connected to the second active device are disposed at the same side of the first active device and the second active device.
    Type: Application
    Filed: January 23, 2013
    Publication date: February 20, 2014
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Jen-Chieh Hsieh, Wei-Kai Huang
  • Through Silicon Via Keep Out Zone Formation Method and System
    Publication number: 20140045332
    Abstract: Keep out zones (KOZ) are formed for a through silicon via (TSV). A device can be placed outside a first KOZ of a TSV determined by a first performance threshold so that a stress impact caused by the TSV to the device is less than a first performance threshold while the first KOZ contains only those points at which a stress impact caused by the TSV is larger than or equal to the first performance threshold. A second KOZ for the TSV can be similarly formed by a second performance threshold. A plurality of TSVs can be placed in a direction that the KOZ of the TSV has smallest radius to a center of the TSV, which may be in a crystal orientation [010] or [100]. A plurality of TSV stress plug can be formed at the boundary of the overall KOZ of the plurality of TSVs.
    Type: Application
    Filed: October 18, 2013
    Publication date: February 13, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Chieh Hsieh, Hung-An Teng, Shang-Yun Hou, Shin-Puu Jeng