Patents by Inventor Chih-Chieh (Steve) Wang

Chih-Chieh (Steve) Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230317830
    Abstract: In a method of manufacturing a semiconductor device a fin structure is formed in which first semiconductor layers and second semiconductor layers are alternately stacked over a substrate. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure that is not covered by the sacrificial gate structure is etched to form a source/drain space. An isolation region is formed at a bottom portion of the source/drain space. A source/drain epitaxial layer is formed over the isolation region in the source/drain space, and a void region in the isolation region is produced between the source/drain epitaxial layer and the substrate to cause electrical isolation between the source/drain region and the substrate.
    Type: Application
    Filed: March 31, 2022
    Publication date: October 5, 2023
    Inventors: Tsung-Lin LEE, Da-Wen LIN, Chih Chieh YEH
  • Publication number: 20230317784
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming a semiconductor fin structure including first semiconductor layers and second semiconductor layers alternatingly stacked, laterally recessing the first semiconductor layers of the semiconductor fin structure to form first notches in the first semiconductor layers, forming first passivation layers on first sidewalls of the first semiconductor layers exposed from the first notches, and forming first inner spacer layers in the first notches.
    Type: Application
    Filed: March 31, 2022
    Publication date: October 5, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Lin LEE, Choh-Fei YEAP, Da-Wen LIN, Chih-Chieh YEH
  • Patent number: 11774497
    Abstract: The present invention discloses an isolation circuit having test mechanism. An isolation circuit component performs signal transmission when a signal that a control terminal receives has an enabling state and performs signal isolation when the signal has a disabling state. The test circuit includes a multiplexer and a control circuit. Under a shifting operation state in a test mode, the control circuit controls the multiplexer to select an operation input terminal to receive and output an isolation control signal having the enabling state to the control input terminal. Under a capturing operation state in the test mode, the control circuit controls the multiplexer to select a test input terminal to receive and output the test signal to the control input terminal. The control circuit further determines whether the isolation circuit performs signal transmission or signal isolation according to the signals at the data input terminal and the data output terminal.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: October 3, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Kuo-Kai Liu, Chih-Chieh Cheng, Pei-Ying Hsueh
  • Publication number: 20230308313
    Abstract: A communication apparatus and an associated method are disclosed. The communication apparatus includes differential input ports; a signal pairing circuit, arranged for coupling the differential input ports to a receiving circuit, wherein when the signal pairing circuit operates in a first mode, a positive input port and a negative input port of the differential input ports correspondingly electrically couple to a positive input terminal and a negative input terminal of the receiving circuit, when the signal pairing circuit operates in a second mode, the positive input port and the negative input port of the differential input ports correspondingly electrically couple to the negative input terminal and the positive input terminal of the receiving circuit; a processor circuit, arranged for determining whether the decoded signal includes a specific code before the timer is time out and generating a determination result; and control the signal pairing circuit according to the determination result.
    Type: Application
    Filed: March 19, 2023
    Publication date: September 28, 2023
    Inventors: TE LUNG FANG, CHIH CHIEH YEN, JEN-HAO YEH, WEI-YI WEI
  • Patent number: 11770728
    Abstract: A method for performing measurement scheduling control by a user equipment (UE) and associated apparatus are provided. The method may include: establishing a connection with a base station on a cell of the base station, wherein the UE is configured to perform measurement on at least one reference signal of at least one cell comprising the cell; obtaining, by a modulator-demodulator (Modem) in the UE, sensor information from a sensor system within the UE through a communication interface between the sensor system and the Modem; and controlling periodicity of a measurement cycle of the measurement according to the sensor information in order to reduce power consumption of the UE.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: September 26, 2023
    Assignee: MEDIATEK INC.
    Inventors: Chih-Chieh Lai, Jianwei Zhang, Ming-Chun Chiang, Mingjun Xu, Lun-Han Chang
  • Patent number: 11769032
    Abstract: An embodiment of the present invention provides a counting information updating method for a portable electronic device having a plurality of spheres connected with each other. The method includes: generating an angular velocity signal by a first sensor of the portable electronic device and generating an acceleration signal by a second sensor of the portable electronic device in response to a sphere moving operation; and estimating counting information corresponding to the sphere moving operation by using the angular velocity signal with an assistance of the acceleration signal.
    Type: Grant
    Filed: December 24, 2020
    Date of Patent: September 26, 2023
    Assignee: Acer Incorporated
    Inventors: Chih-Chieh Chien, Yi-Chun Chung, Pei-Wen Jung, Yen-Ming Hsu
  • Publication number: 20230298635
    Abstract: A method for forming sense amplifiers of a memory device includes: determining a type of each bitline selector used to provide a data signal to a corresponding sense amplifier; forming a plurality of separate active areas in a substrate of the memory device along one of a column direction and a row direction according to the type of the bitline selector, the substrate including a plurality of cell columns, each of the cell columns having a plurality of memory cells arranged along the column direction, each of the active areas being formed across a boundary between two adjacent cell columns and located within the adjacent cell columns; and arranging a plurality of gate structures on the active areas to form transistors of the sense amplifiers, each gate structure extending in the row direction.
    Type: Application
    Filed: March 17, 2022
    Publication date: September 21, 2023
    Inventors: CHENG-CHANG CHEN, CHIH-CHIEH CHIU, CHUN-YEN LIN
  • Publication number: 20230286044
    Abstract: Method of forming a switch bracket of a hinge for a two-body information handling system, including mixing metal powders and binders to form a blended mix; pelletizing the blended mix to form feedstock; injecting the feedstock into a switch bracket mold cavity to form a first article of the switch bracket; de-binding the first article to remove the binders from the first article forming a second article of the switch bracket; and sintering the second article by shrinking the second article to form the switch bracket.
    Type: Application
    Filed: March 11, 2022
    Publication date: September 14, 2023
    Inventors: CHIH-CHIEH CHANG, WEI-YI LI, CHUN-MIN HE
  • Patent number: 11746170
    Abstract: The present invention relates to an ethylene-vinyl alcohol copolymer (EVOH) resin composition, an EVOH film formed therefrom, and a multilayer structure containing the same. The core void volume (Vvc) of the surface of the EVOH resin composition is more than 0.010 ?m3/?m2 and less than 50 ?m3/?m2; or its surface pole height (Sxp) is more than 0.010 ?m and less than 9.0 ?m. The invention can reduce the torque output during processing, reduce the adsorption of fine powder on the surface caused by static electricity generated on the surface of the EVOH, and provide good film thickness uniformity.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: September 5, 2023
    Assignee: CHANG CHUN PETROCHEMICAL CO., LTD.
    Inventors: Chih Chieh Liang, Wen Hsin Lin
  • Patent number: 11740260
    Abstract: A pogo pin-free testing device for IC chip test includes a load board, a ceramic interposer disposed on the load board, and copper core balls. The ceramic interposer has first and second surfaces and connecting points, and the second surface of the ceramic interposer faces the load board. Each connecting point has through holes penetrating the first and second surfaces, and an inner sidewall surface thereof has a metallization layer. The metallization layer is extended to a portion of the first surface and a portion of the second surface. In each of the connecting points, an area of an extending portion of the metallization layer extended to the second surface is less than an area of an extending portion of the metallization layer extended to the first surface. The copper core balls are disposed between the load board and the through holes of each connecting point of the ceramic interposer.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: August 29, 2023
    Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chieh Liao, Yu-Min Sun, Chih-Feng Cheng, Pei-Shiou Huang
  • Patent number: 11742352
    Abstract: A semiconductor device includes first and second source/drain structures, a channel layer, a gate structure, and an epitaxial layer. The channel layer is above the first source/drain structure. The second source/drain structure is above the channel layer. The gate structure is on a first side surface of the channel layer. The epitaxial layer forms a P-N junction with a second side surface of the channel layer.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Li Chiang, Szu-Wei Huang, Chih-Chieh Yeh, Yee-Chia Yeo
  • Publication number: 20230268337
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a fin disposed in a first region of the semiconductor device, channel members disposed in a second region of the semiconductor device and stacked in a vertical direction, first and second metal gates disposed on a top surface of the fin, a third metal gate wrapping around each of the channel members, a first implant region in the fin with a first conductivity type, and a second implant region in the fin with a second conductivity opposite the first conductivity type. The fin includes first and second type epitaxial layers alternatingly disposed in the vertical direction. The first and second type epitaxial layers have different material compositions. The first type epitaxial layers and the channel members have the same material composition.
    Type: Application
    Filed: April 24, 2023
    Publication date: August 24, 2023
    Inventors: Chih-Hung Wang, Chih Chieh Yeh, Zi-Ang Su, Chia-Ju Chou, Ming-Shuan Li
  • Publication number: 20230261009
    Abstract: An electronic device having a peripheral area and a non-peripheral area adjacent to the peripheral area is provided. The electronic device includes a flexible substrate, a first conductive layer disposed on the flexible substrate and disposed in the peripheral area and the non-peripheral area, an organic layer disposed in the non-peripheral area and on the first conductive layer, a second conductive layer disposed on the first conductive layer, and an organic structure disposed between the first conductive layer and the second conductive layer in the peripheral area. The organic layer and the organic structure are the same material layer.
    Type: Application
    Filed: April 21, 2023
    Publication date: August 17, 2023
    Inventors: Ti-Chung CHANG, Chih-Chieh WANG, Chien-Chih CHEN
  • Publication number: 20230246602
    Abstract: An improved architecture for a radio frequency (RF) power amplifier, impedance matching network, and selector switch. One aspect of embodiments of the invention is splitting the functionality of a final stage impedance matching network (IMN) into two parts, comprising a base set of off-chip IMN components and an on-chip IMN tuning component. The on-chip IMN tuning component may be a digitally tunable capacitor (DTC). In one embodiment, an integrated circuit having a power amplifier, an on-chip IMN tuner, and a selector switch is configured to be coupled to an off-chip set of IMN components. In another embodiment, an integrated circuit having an on-chip IMN tuner and a selector switch is configured to be coupled through an off-chip set of IMN components to a separate integrated circuit having an RF power amplifier.
    Type: Application
    Filed: February 2, 2023
    Publication date: August 3, 2023
    Inventors: Tero Tapio Ranta, Chih-Chieh Cheng, Kevin Roberts
  • Publication number: 20230238451
    Abstract: A device includes a plurality of semiconductor fins extending from a substrate. A plurality of first source/drain regions are epitaxially grown from first regions of the semiconductor fins. Adjacent two of the plurality of first source/drain regions grown from adjacent two of the plurality of semiconductor fins are spaced apart by an isolation dielectric. A gate structure laterally surrounds second regions of the plurality of semiconductor fins above the first regions of the plurality of semiconductor fins. A plurality of second source/drain regions are over third regions of the plurality of semiconductor fins above the second regions of the plurality of semiconductor fins.
    Type: Application
    Filed: April 3, 2023
    Publication date: July 27, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Sheng YUN, Shao-Ming YU, Tung-Ying LEE, Chih-Chieh YEH
  • Patent number: 11703244
    Abstract: A testing apparatus including a base and a preheating unit arranged on the base is provided. The preheating unit includes a gas generator, a blocking mechanism and a heating device. The gas generator is configured to discharge air toward the base to form an air wall. The blocking mechanism is located above the air wall and forms a heat preservation space with the air wall. The heating device is arranged in the heat preservation space.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: July 18, 2023
    Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chieh Liao, Yu-Min Sun, Chih-Feng Cheng
  • Publication number: 20230219101
    Abstract: A fluid pipe magnetization unit includes a ferromagnetism casing, a plurality of magnetic rods, and at least one flow limiting element. The magnetic rods include at least one first magnetic rod and at least one second magnetic rod. Inner elements of the first magnetic rod and the second magnetic rod are alternately positioned with opposite magnetic poles in the ferromagnetism casing. The at least one flow limiting element is arranged in at least one weak magnetic area in the ferromagnetism casing to prevent fluid from flowing through the at least one weak magnetic area. In addition, a fluid pipe magnetization device with the same is also disclosed herein.
    Type: Application
    Filed: May 20, 2022
    Publication date: July 13, 2023
    Inventors: Ching-Ho YU, Yung-Hsiang WANG, Chih-Chieh MO
  • Publication number: 20230219136
    Abstract: A waste magnet regeneration method includes the following steps. First, waste magnets and auxiliary alloys are provided, pre-treat the waste magnets, hydrogen decrepitating and sieving the waste magnets and the auxiliary alloys to form main alloy powders and auxiliary alloy powders. The main alloy powders and the auxiliary alloy powders are mixed in a predetermined ratio to form a mixture, and then the mixture is subjected to the jet mill pulverization, magnetic field alignment compacting, sintering and aging treatment to obtain a regenerated magnet.
    Type: Application
    Filed: June 20, 2022
    Publication date: July 13, 2023
    Inventors: Ching-Ho YU, Chih-Chieh MO
  • Patent number: 11699457
    Abstract: A testing system includes a testing apparatus and a crack noise monitoring device. The testing apparatus includes a testing stage and an element pickup module for pressing a semiconductor element on the testing stage. The crack noise monitoring device includes a database unit, a sound conduction set, a voiceprint generation unit and a processing unit. The database unit has a first voiceprint pattern. The sound conduction set is connected to the voiceprint generation unit and the testing apparatus for transmitting a sound wave from the semiconductor element to the voiceprint generation unit. The voiceprint generation unit receives and converts the sound wave into a second voiceprint pattern. The processing unit is electrically connected to the voiceprint generating unit and the database unit for determining whether the first voiceprint pattern is identical to the second voiceprint pattern.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: July 11, 2023
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chieh Liao, Chih-Feng Cheng, Yu-Min Sun
  • Publication number: 20230215853
    Abstract: A method includes forming multiple photonic devices in a semiconductor wafer, forming a v-shaped groove in a first side of the semiconductor wafer, forming an opening extending through the semiconductor wafer, forming multiple conductive features within the opening, wherein the conductive features extend from the first side of the semiconductor wafer to a second side of the semiconductor wafer, forming a polymer material over the v-shaped groove, depositing a molding material within the opening, wherein the multiple conductive features are separated by the molding material, after depositing the molding material, removing the polymer material to expose the v-shaped groove, and placing an optical fiber within the v-shaped groove.
    Type: Application
    Filed: March 13, 2023
    Publication date: July 6, 2023
    Inventors: Chih-Chieh Chang, Chung-Hao Tsai, Chuei-Tang Wang, Hsing-Kuo Hsia, Chen-Hua Yu