Abstract: A semiconductor structure is provided. The semiconductor structure includes a first substrate, a device layer, a first dielectric layer, a second dielectric layer, a second substrate, and a circuit layer. The device layer is disposed on the first substrate. The first dielectric layer is disposed on the device layer. The second dielectric layer is disposed on the first dielectric layer. The second substrate is disposed on the second dielectric layer. The circuit layer is disposed on the second substrate.

Abstract: A host system is coupled to a storage device and manages completion queues (CQs) for the storage device. The host system includes a host controller and memory that stores submission queues (SQs) and the CQs. The host controller fetches a command from a given SQ that corresponds to a target CQ. The host controller saves the command in an SQ internal buffer of the host controller, calculates an available capacity (AC) associated with the given SQ for the host system to store a response to the command from the storage device, and sends the command to the storage device when the available capacity is non-zero. The available capacity is calculated based on, at least in part, available slots in the target CQ.

Abstract: An information processing method controls a CT scanner such that the method includes, but is not limited to, determining an X-ray irradiation period from an electrocardiogram acquired from an electrocardiography device attached to a living object to be imaged, by processing the electrocardiogram at multiple different cardiac phases; performing, by controlling a CT gantry including and rotatably supporting an X-ray source and an X-ray detector, a diagnostic CT scan in the determined X-ray irradiation period, of at least a part of the heart region, to obtain a CT image; and causing a display unit to display the obtained CT image. The method can be performed at least by an information processing apparatus including processing circuitry and/or computer instructions stored in a non-transitory computer readable storage medium for performing the method.

Abstract: A display panel and a spliced display are provided. The display panel includes a substrate, a plurality of light-emitting elements, a driving circuit, and an optical sensor. The substrate includes a through hole, and the through hole includes a hole. The plurality of the light-emitting elements are disposed on the substrate. The through hole is located in a region between two of the plurality of the light-emitting elements. The driving circuit is disposed on the substrate and electrically connected to the plurality of the light-emitting elements. The optical sensor is disposed corresponding to the through hole and receives sensing light through the hole. The width W of the hole meets the equation of H?W<D. H is the depth of the hole, and D is the distance between the two of the plurality of the light-emitting elements.

Abstract: The invention encompasses hydrogels, monomer precursors of the hydrogels, methods for the preparation thereof, and methods of use therefor. The linking of monomers can take place using non-radical, bioorthogonal reactions such as copper-free click-chemistry.

Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).

Abstract: A semiconductor structure includes a first semiconductor layer having an upper portion over a lower portion, a source/drain feature over the upper portion of the first semiconductor layer, a first contact structure under the lower portion of the first semiconductor layer and electrically connected to the lower portion of the first semiconductor layer. The lower portion is more heavily doped with first dopants than the upper portion. The first dopants are of a first conductivity-type. The source/drain feature includes second dopants of a second conductivity-type opposite to the first conductivity-type.

Abstract: The present application provides a circuit board and a manufacturing method thereof. The manufacturing method includes: providing a stacked board; the stacked board includes a third conducting circuit, a second substrate, a first conducting circuit, a first substrate, and a second conducting circuit, which are stacked disposed in that order; defining several through holes on a surface of the stacked board along a stacked direction of the stacked board; and manufacturing antenna conductors in the through holes. The antenna conductors are disposed in the through holes on a surface of the stacked board, the antenna conductors on different layers are connected to corresponding conducting circuits, some of the antenna conductors are directly connected with the conducting circuit. A loss of signals while transmitting is reduced, and the circuit board including the antenna structure is changed from an up-down structure into a left-right structure for reducing a board thickness.

Abstract: A method for manufacturing a fan-out chip packaging structure with decreased use of a crack-inducing hot-soldering process includes a first carrier plate with first and a second outer wiring layers. Two first conductive posts are formed on the first outer wiring layer, one end of each post is electrically connected to the first outer wiring layer. A receiving groove is formed between first conductive posts, and a sidewall of each post is surrounded by a first insulating layer. An embedded component is laid in the receiving groove and a second carrier plate is formed on the first insulating layer, wherein the second carrier plate carries third and fourth outer wiring layers. A first outer component is connected to the second outer wiring layer, and a second outer component is connected to the fourth outer wiring layer.

Abstract: An electric device includes a semiconductor assembly, a circuit board, first conductive pads and second conductive pads. The circuit board has a chip-mounted area with a rectangular shape. The first conductive pads are arranged in a center zone or all corner zones of the chip-mounted area, and the second conductive pads are arranged within the rest in the chip-mounted area. The first conductive pads are respectively soldered to one part of solder joints of the semiconductor assembly through first solder-ball portions, and the second conductive pads are respectively soldered to another part of the solder joints of the semiconductor assembly through second solder-ball portions. Each of the second conductive pads is sized smaller than one of the first conductive pads, and a maximum width of each of the second solder-ball portions is greater than a maximum width of each of the first solder-ball portions.

Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

Abstract: A tissue repair device and a method for using the same are provided. The tissue repair device includes a body portion and at least one wire. The body portion includes an inner layer and an outer layer. The inner layer is close to a tissue, wherein the inner layer includes a hydrophilic structure, and the outer layer includes a hydrophobic structure. The wire is connected to the body portion to fix the body portion to the tissue.

Abstract: Provided herein are chemical-mechanical planarization (CMP) systems and methods to reduce metal particle pollution on dressing disks and polishing pads. Such methods may include contacting a dressing disk and at least one conductive element with an electrolyte solution and applying direct current (DC) power to the dressing disk and the at least one conductive element.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. The method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. The hydrophobic layer is formed on a sidewall surface of the dielectric layer. The method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.

Abstract: An inspecting device including a carrier, multiple telescopic probes, a locking component and a conductive structure is provided. The carrier has a through hole and a ground pad corresponding to the through hole. The through hole penetrates from the first surface to the second surface of the carrier, and the ground pad is disposed on the second surface. The telescopic probes are disposed in parallel on the first surface of the carrier. The locking component passes through the through hole and is disposed between two adjacent telescopic probes of the multiple telescopic probes. The locking component includes a screw. A head of the screw has a first pitch and a second pitch, and a density of the first pitch is different from a density of the second pitch. The conductive structure is partially embedded in the locking component, and the conductive structure, the locking component and the ground pad are electrically connected.

Abstract: A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. A high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. A metal layer is formed along opposing sidewalls of the high-k dielectric layer. The metal layer includes a first material. The spacing area is free of the first material.

Abstract: A thermal peak suppression device includes a heat dissipation fin set, a heat dissipator, a thermal phase change material, a filling gas, a fin-array frame and a capillary tube. The heat dissipator includes a thermal conductive block thermally coupled to the heat dissipation fin set, and a closed cavity formed inside the thermal conductive block to have a hot zone and a cold zone. The thermal phase change material is disposed within the hot zone. The filling gas is disposed within the cold zone. The fin-array frame is connected to the thermal conductive block within the cold zone. Two opposite ends of the capillary tube are respectively located within the cold zone and the hot zone. When the thermal phase change material is transformed into a liquid state, the thermal phase change material is sent to the hot zone through the capillary tube.

Abstract: A power detector with wide dynamic range. The power detector includes a linear detector, followed by a voltage-to-current-to-voltage converter, which is then followed by an amplification stage. The current-to-voltage conversion in the converter is performed logarithmically. The power detector generates a desired linear-in-dB response at the output. In this power detector, the distribution of gain along the signal path is optimized in order to preserve linearity, and to minimize the impact of offset voltage inherently present in electronic blocks, which would corrupt the output voltage. Further, the topologies in the sub-blocks are designed to provide wide dynamic range, and to mitigate error sources. Moreover, the temperature sensitivity is designed out by either minimizing temperature variation of an individual block such as the v-i-v detector, or using two sub-blocks in tandem to provide overall temperature compensation.

Abstract: A package assembly and a manufacturing method thereof are provided. The package assembly includes a first package component and an optical signal port disposed aside the first package component. The first package component includes a first die including an electronic integrated circuit, a first insulating encapsulation laterally covering the first die, a redistribution structure disposed on the first die and the first insulating encapsulation, and a second die including a photonic integrated circuit and electrically coupled to the first die through the redistribution structure. The optical signal port is optically coupled to an edge facet of the second die of the first package component.

Abstract: Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a vertical stack of channel members disposed over a substrate, a gate structure wrapping around each channel member of the vertical stack of channel members, a dielectric feature disposed directly on the substrate and in direct contact with a portion of the vertical stack of channel members, and a source/drain feature disposed directly on the dielectric feature and electrically coupled to a remaining portion of the vertical stack of channel members.