Patents by Inventor Ching-An Chung

Ching-An Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220197543
    Abstract: A method for assigning a plurality of channel of a storage device for stream data writing, a storage device and a storage medium are provided. The method includes: providing global available channel status data and stream suitable channel status data for one of a plurality of streams by a controller of the storage device for processing stream data writing for the plurality of streams; generating stream available channel status data for the one of the plurality of streams, based on the global available channel status data and the stream suitable channel status data for the stream; selecting at least one available channel of the plurality of channels according to the stream available channel status data; and updating the global available channel status data with respect to the at least one available channel selected and updating the stream suitable channel status data for one of the plurality of streams.
    Type: Application
    Filed: November 18, 2021
    Publication date: June 23, 2022
    Applicant: SK hynix Inc.
    Inventors: CHING-CHUNG LAI, LIAN-CHUN LEE, CHUN-SHU CHEN
  • Patent number: 11366283
    Abstract: The present disclosure provides a small and well-focused lens driving device, a camera including the lens driving device, and a portable electronic apparatus. The lens driving device includes a fixing base, a cover, a lens holder, a support frame, a support member, and a shape memory alloy portion. In the lens driving device, a receiving space is defined by the fixing base and the cover. The lens holder configured to receive a lens, as well as the support frame, the support member, and the shape memory alloy portion that cause the lens holder to move freely in an optical axis direction are provided in the receiving space. The shape memory alloy portion has a shape memory alloy and a crimping lug, and the shape memory alloy portion is provided on the fixing base and the support frame to cause the lens holder to move freely in the optical axis direction.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: June 21, 2022
    Assignee: AAC Optics Solutions Pte. Ltd.
    Inventor: Ching-Chung Chiu
  • Patent number: 11367788
    Abstract: A semiconductor device structure is provided. A first well region with a first type of conductivity is formed over a semiconductor substrate. A second well region with a second type of conductivity is formed over the semiconductor substrate. A well region is formed over the semiconductor substrate and between the first and second well regions. A first gate structure is disposed on the well region and partially over the first and second well regions. A drain region is in the first well region. A source region and a bulk region are in the second well region. The drain region, the source region and the bulk region have the first type of conductivity. A second gate structure is disposed on the second well region, and separated from the first gate structure by the source region and the bulk region.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: June 21, 2022
    Assignee: MEDIATEK INC.
    Inventors: Jing-Chyi Liao, Ching-Chung Ko, Zheng Zeng
  • Publication number: 20220182047
    Abstract: A deskew circuit for a differential signal is provided. A first common mode voltage generating circuit generates a first common mode voltage signal according to first and second differential input signals. A voltage buffer circuit is coupled to the first common mode voltage generating circuit and has an input impedance higher than a preset value, and buffers the first common mode voltage signal and the first and second differential input signals to generate a second common mode voltage signal, a third differential input signal, and a fourth differential input signal. A second common mode voltage generating circuit is coupled to the voltage buffer circuit and generates a third common mode voltage signal according to the third and fourth differential input signals. An output circuit generates a deskew output signal according to the third and fourth differential input signals and the second and third common mode voltage signals.
    Type: Application
    Filed: November 26, 2021
    Publication date: June 9, 2022
    Applicant: ALi Corporation
    Inventors: Ming-Ta Lee, Ching-Chung Cheng
  • Publication number: 20220159127
    Abstract: In a voice signal relay and transfer method for a voice call between a radio voice terminal and a remote device includes, a radio voice signal is received from the radio voice terminal and converting the radio voice signal into a digital voice signal. The digital voice signal is further converted into a group of voice packets in a streaming form. Then the group of voice packets is transmitted to a streaming server via a mobile communication network. The group of voice packets is further transferred from the streaming server to the remote device in a streaming form.
    Type: Application
    Filed: December 7, 2020
    Publication date: May 19, 2022
    Inventors: SHIH CHIEH SU, CHING-CHUNG CHIANG, YI PENG CHENG
  • Publication number: 20220148711
    Abstract: Systems with a contouring method are provided for contouring one or more targets that correspond to specific organs and/or tumors in a three-dimensional medical image of a patient using neural networks. The contouring system includes a storage unit, a processing unit, and a plurality of modules that are computer operable. The processing unit is used to obtain the image, and then to generate one or more contouring images using a contouring method. The contouring method includes enhancing image features and improving contouring accuracy using an image preprocessing module, and extracting a plurality of multi-scale image representations and expanding these representations to one or more contouring images using a neural network-based contouring module.
    Type: Application
    Filed: June 29, 2021
    Publication date: May 12, 2022
    Inventors: Kuei-Hong KUO, Yi-Ting PENG, Ching-Chung KAO, Ai-Ling HSU, Yu-Ren YANG, Pei-Wei SHUENG, Chun-You CHEN, Kuan-Chieh HUANG
  • Patent number: 11330397
    Abstract: A position tracking system for Tags to collect relative proximity to other Tags using received signal strength, with methods to reduce power consumption with controlled degradation in overall system performance such as location accuracy and frequency of location updates. Configurable parameters for control of tag functions facilitate performance tradeoffs against application requirements. System architecture using mobile phone and gateway for uploading data enables efficient upload of tag data without user intervention. Applications of the disclosure include self-quarantine, contact tracing, mother-infant pairing, location history tracking, and personnel-asset usage monitoring.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: May 10, 2022
    Assignee: TraceSafe Technologies, Inc.
    Inventors: Francis Antony, Suresh Singamsetty, Dennis Ching Chung Kwan, Sujith Balakrishnan, Manu Velayudhan
  • Publication number: 20220100650
    Abstract: The memory system comprises nonvolatile memory devices each including plural superblocks and a controller. The controller is configured to select a victim superblock including a smaller number of valid pages than any among remaining superblocks, exchange a greater-valid-pages block with a smaller-valid-pages block, and control the memory device to perform a garbage collection operation on the victim superblock, wherein the greater-valid-pages block is included in the victim superblock and the smaller-valid-pages block is included in one among the remaining superblocks, and wherein the smaller-valid-pages block has a smaller number of valid pages than the greater-valid-pages block.
    Type: Application
    Filed: March 24, 2021
    Publication date: March 31, 2022
    Inventors: Ching-Chung LAI, Lian-Chun LEE, Chun-Shu CHEN
  • Publication number: 20220085210
    Abstract: A semiconductor device includes a semiconductor substrate, a recess, a first gate oxide layer, and a gate structure. The semiconductor substrate includes a first region and a second region adjacent to the first region. The recess is disposed in the first region of the semiconductor substrate, and an edge of the recess is located at an interface between the first region and the second region. At least a part of the first gate oxide layer is disposed in the recess. The first gate oxide layer includes a hump portion disposed adjacent to the edge of the recess, and a height of the hump portion is less than a depth of the recess. The gate structure is disposed on the first region and the second region of the semiconductor substrate, and the gate structure overlaps the hump portion of the first gate oxide layer in a vertical direction.
    Type: Application
    Filed: October 12, 2020
    Publication date: March 17, 2022
    Inventors: Chang-Po Hsiung, Ching-Chung Yang, Shan-Shi Huang, Shin-Hung Li, Nien-Chung Li, Wen-Fang Lee, Chiu-Te Lee, Chih-Kai Hsu, Chun-Ya Chiu, Chin-Hung Chen, Chia-Jung Hsu, Ssu-I Fu, Yu-Hsiang Lin
  • Publication number: 20220075799
    Abstract: A terminal, a storage medium, and a database synchronization method thereof are disclosed. The database synchronization method includes reading data from a first database and capturing a dynamic data log in the first database; joining data to a waiting queue read from the first database; determining a dislocation category of the data in the waiting queue, and rearranging the dislocation data in the waiting queue into a first category according to the dynamic data log; and synchronizing the rearranged data to a second database. According to the database synchronization method provided by the present invention caches the data read from the first database to the waiting queue, and dislocation data in the waiting queue is rearranged and then synchronized to the second database, so that a problem of poor data identity after database synchronization is avoided.
    Type: Application
    Filed: December 3, 2020
    Publication date: March 10, 2022
    Inventors: Yeh-Ching Chung, Yuan YU
  • Patent number: 11264378
    Abstract: A device includes a dielectric layer, an interlayer metal pad in the dielectric layer, a first capacitor over the interlayer metal pad, and a second capacitor over the dielectric layer. The first capacitor includes a first bottom capacitor electrode over and in contact with the interlayer metal pad, a first top capacitor electrode, and a first inter-electrode dielectric layer between the first bottom capacitor electrode and the first top capacitor electrode. The second capacitor includes a second bottom capacitor electrode over and in contact with the dielectric layer, a second top capacitor electrode, and a second inter-electrode dielectric layer between the second bottom capacitor electrode and the second top capacitor electrode.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: March 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Yu Chen, Chih-Ping Chao, Chun-Hung Chen, Chung-Long Chang, Kuan-Chi Tsai, Wei-Kung Tsai, Hsiang-Chi Chen, Ching-Chung Hsu, Cheng-Chang Hsu, Yi-Sin Wang
  • Patent number: 11262398
    Abstract: The present disclosure provides a testing fixture. The testing fixture includes a carrier, a plurality of sets of electrical lines and a plurality of electrical lines. The carrier includes a base and a frame extending along an upper surface of the base. The base and the frame define a first recess, a second recess extending longitudinally from the first recess, and a third recess extending transversely from the first recess. The plurality of sets of electrical contacts are disposed on the base and arranged in a rotationally symmetrical manner, and the electrical lines are electrically connected to the plurality of sets of electrical contacts.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: March 1, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ching-Chung Wang, Jui-Hsiu Jao
  • Publication number: 20220059697
    Abstract: A method of fabricating a semiconductor device includes: forming a first transistor including: forming a plurality of lightly doped regions in a substrate; forming a first gate structure on the substrate, the first gate structure covering portions of the plurality of lightly doped regions and a portion of the substrate; forming first spacers on sidewalls of the first gate structure; forming doped region in the lightly doped regions; forming an etching stop layer on the substrate; patterning the etching stop layer and the first gate structure to form a second gate structure, and to form a plurality of trenches between the second gate structure and the first spacers; and forming a first dielectric layer on the substrate to cover the etching stop layer and fill the plurality of trenches. The first dielectric layer filled in the trenches is used as virtual spacers.
    Type: Application
    Filed: October 7, 2020
    Publication date: February 24, 2022
    Applicant: United Microelectronics Corp.
    Inventor: Ching-Chung Yang
  • Publication number: 20220059662
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first well, a second well, an isolation structure, a first field plate, a gate structure, a drain structure, and a source structure. The first well and the second well adjoin each other. The first well and the second well are disposed in the substrate. The isolation structure is disposed on the first well. The first field plate is disposed on the isolation structure. The gate structure crosses the first well and the second well, and an opening is defined between the first field plate and the gate structure to expose an edge of the isolation structure adjacent to the gate structure. The drain structure is disposed in the first well. The source structure is disposed in the second well.
    Type: Application
    Filed: August 18, 2020
    Publication date: February 24, 2022
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Yi-Ching CHUNG, Jui-Chun CHANG, Fu-Chun TSENG, Yu-Ping HO
  • Publication number: 20220008601
    Abstract: An air purifier includes a housing, a filter unit and a sterilization unit. The housing has an air outlet and an air inlet under the air outlet. A filtering chamber is formed in the housing by the air outlet and the air inlet. The filtering chamber has a first chamber and a second chamber. The filter unit is disposed in the first chamber. The sterilization unit is disposed in the filtering chamber. A fan is disposed in the second chamber of the housing and over the sterilization unit. The fan is used for sucking air outside the housing, passing the air through the filter unit and the sterilization unit and emitting the air. This can accomplish an object of air purification.
    Type: Application
    Filed: July 13, 2020
    Publication date: January 13, 2022
    Inventors: San-Hsi Wang, Ching-Chung Wang
  • Publication number: 20210404633
    Abstract: A backlight module and a display device are provided. The backlight module includes a light source structure and at least one optical film. The optical film is disposed above the light source structure. The optical film includes a main body and plural optical structures. The optical structures are disposed on the main body. Each of the optical structures is a tapered structure. Each of the optical structures has plural side surfaces, and a portion of light emitted from the light source structure is guided toward plural primary directions when passing through the side surfaces of the optical structures, and therefore the light emitted from the light source is no longer concentrated on the top of each of the optical structures.
    Type: Application
    Filed: September 9, 2021
    Publication date: December 30, 2021
    Inventors: Yen-Chuan CHU, Chia-Yin CHANG, Chin-Ting WENG, Yi-Ching CHUNG, Hao CHEN
  • Patent number: 11209477
    Abstract: The present disclosure provides a testing fixture for holding a device under test (DUT). The testing fixture includes a base, a frame, a recessed portion, a plurality of sets of electrical contacts and a plurality of electrical lines. The frame extends upward along an outer perimeter of an upper surface of the base. The recessed portion is surrounded by the frame and the upper surface of the base, and the DUT is received in the recessed portion. The plurality of sets of electrical contacts are disposed on the recessed portion and arranged in a rotationally symmetrical manner, wherein a plurality of plated through holes of the DUT are in contact with one set of the electrical contacts after the DUT is assembled with the testing fixture.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: December 28, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ching-Chung Wang, Jui-Hsiu Jao
  • Publication number: 20210391274
    Abstract: A semiconductor device includes: a first semiconductor structure; a second semiconductor structure on the first semiconductor structure; an active region between the first semiconductor structure and the second semiconductor structure, wherein the active region includes multiple alternating well layers and barrier layers, wherein each of the barrier layers has a band gap, the active region further includes an upper surface facing the second semiconductor structure and a bottom surface opposite the upper surface; an electron blocking region between the second semiconductor structure and the active region, wherein the electron blocking region includes a band gap, and the band gap of the electron blocking region is greater than the band gap of one of the barrier layers; a first aluminum-containing layer between the electron blocking region and the active region, wherein the first aluminum-containing layer has a band gap greater than the band gap of the electron blocking region; a confinement layer between the fi
    Type: Application
    Filed: June 22, 2021
    Publication date: December 16, 2021
    Inventors: Yung-Chung PAN, Chang-Yu TSAI, Ching-Chung HU, Ming-Pao CHEN, Chi SHEN, Wei-Chieh LIEN
  • Patent number: 11199722
    Abstract: Provided is a lens driver movable in a direction parallel to an optical axis, arranged on a lens driver movable in a plane orthogonal to the optical axis, and accommodated in a casing. The lens driver includes: a fixture base, a support frame A, a lens module, a spring piece, a first driving coil, a magnet and a yoke. The lens driver includes: a base; a connection terminal and a conductive member A arranged on the base; a support frame B supported by a support part; a conductive member B arranged on the support frame; a center holding part for keeping the base and the support frame B at a center of the optical axis; a second driving coil arranged on the base; and a magnetic detecting element. The lens driver provided can achieve purposes of anti-image dithering and simplifying assembly to obtain good image quality.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: December 14, 2021
    Assignee: AAC Optics Solutions Pte. Ltd.
    Inventors: Ching-Chung Chiu, Shikama Kazuo
  • Publication number: 20210378616
    Abstract: The present invention discloses a method and a system of vertebral compression fracture detection. The method of vertebral compression fracture detection includes: recombining a plurality of anatomical images captured in at least a spine segment of a target individual into a 3D image; using a multi-planar reconstruction method to reformat the 3D image to obtain at least one sagittal reformatted image; using a classification model to determine whether the sagittal reformatted image covers the middle section of the vertebral column or not; using a vertebral detection method to detect each vertebral body in the sagittal reformatted image covering the middle section of the vertebral column; using a keypoint localization method to localize a plurality of keypoints of each vertebral body which was detected in the sagittal reformatted image; evaluating the compression fracture grade of each vertebral body in the sagittal reformatted image.
    Type: Application
    Filed: April 6, 2021
    Publication date: December 9, 2021
    Inventors: Wing P. CHAN, Ai-Ling HSU, Kuan-Chieh HUANG, Yi-Ting PENG, Ching-Chung KAO