Patents by Inventor Chun Chieh

Chun Chieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070231198
    Abstract: A method of treating an instrument after contamination of a surface thereof includes the steps of covering the surface with a foam and maintaining the foam on the surface to keep the surface moist prior to cleaning the instrument to prevent foreign matter thereon from becoming dried on and more difficult to remove during cleaning. The foam includes hydrogen peroxide, dissolves blood and provides antimicrobial effect.
    Type: Application
    Filed: November 30, 2006
    Publication date: October 4, 2007
    Inventors: Szu-Min Lin, Robert C. Platt, Chun-Chieh J. Tseng, Robert F. Mosher
  • Publication number: 20070231200
    Abstract: A method and system of treating an instrument after contamination of a surface thereof includes the steps of covering the surface with a hydrogen peroxide foam and then subsequently treating the foam with a defoaming agent and a neutralizing agent for hydrogen peroxide.
    Type: Application
    Filed: May 31, 2006
    Publication date: October 4, 2007
    Inventors: Szu-Min Lin, Robert Platt, Chun-Chieh Tseng
  • Publication number: 20070221810
    Abstract: A rotation mechanism of a television includes a rotation unit, a box, a frame which is connected on the box and connected with the television, and a driving unit. The driving unit has a stationary fan-shaped rack with a positioning rod and a pivot. The rack is connected to the rotation unit and box is rotated about the rack when the driving unit is activated so that the rotation unit and the frame are rotated. By this arrangement, the television is rotated with the rotation unit.
    Type: Application
    Filed: March 22, 2006
    Publication date: September 27, 2007
    Inventor: Chun-Chieh Liao
  • Publication number: 20070223036
    Abstract: A medium processing apparatus with queue management function includes a queue managing unit, and a connection port, an operation interface and a medium processing unit, all of which are connected to the queue managing unit. The queue managing unit receives, through the connection port, and stores a plurality of job signals coming from a network system. The operation interface generates and outputs a control signal to the queue managing unit according to a set of control instructions inputted by a user. The queue managing unit outputs at least one of the job signals to the medium processing unit according to the control signal so that the medium processing unit performs an image processing procedure on a medium.
    Type: Application
    Filed: March 16, 2007
    Publication date: September 27, 2007
    Inventor: Chun-Chieh Liao
  • Publication number: 20070217156
    Abstract: An electronic device has a first circuit board, a first fan, a second circuit board, a first heat sink, and a first air ventilation duct. The first fan and the first circuit board are electrically connected together. The second circuit board is electrically connected to the first circuit board; the first heat sink is electrically connected to the second circuit board; and the first air ventilation duct is connected to the first fan and the first heat sink. The first heat sink introduce the heat generated by the electronic element on the second circuit board to the first fan for better cooling performance. Therefore, the present invention requires only the first fan and the second fan, but is able to provide high cooling efficiencies with a low noise signature.
    Type: Application
    Filed: October 11, 2006
    Publication date: September 20, 2007
    Applicant: ASUSTEK COMPUTER INC.
    Inventors: Chun-Chieh Wu, Hung-Chun Chu, Hsi-Feng Lin
  • Patent number: 7271609
    Abstract: Described is a method for automatically generating a wafer prober file whereby testing parameters and die identities can be established for testing a complete semiconductor wafer and whereby acceptable or rejected dies can be identified and correlated later with where the good or bad dies are physically located on a wafer-under-test.
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: September 18, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kevin Liao, Edward Chen, Win Hung, Jumbo Chuang, Chang-Chi Hsu, Chia-Ping Liu, Chun-Chieh Hsiao
  • Publication number: 20070212606
    Abstract: A family of Li-ion battery cathode materials and methods of synthesizing the materials. The cathode material is a defective crystalline lithium transition metal phosphate of a specific chemical form. The material can be synthesized in air, eliminating the need for a furnace having an inert gas atmosphere. Excellent cycling behavior and charge/discharge rate capabilities are observed in batteries utilizing the cathode materials.
    Type: Application
    Filed: March 8, 2006
    Publication date: September 13, 2007
    Inventor: Chun-Chieh Chang
  • Publication number: 20070214460
    Abstract: A method for dynamic event matching. A domain model for each domain is defined. Individual requirements and preferences of a user are modeled to create a personal model. Dynamic requirements of a specific domain for the user are modeled. A dynamic event is generated. The dynamic event is obtained using an information server for format transformation to create an event model. The personal model is matched with the event model using a content-based method according to the domain model and the dynamic event. The user is informed of the matching results. The matching results are adjusted according to user feedback.
    Type: Application
    Filed: January 18, 2006
    Publication date: September 13, 2007
    Inventors: Tse-Ming Tsai, Chin-Cheng Wu, Chun-Chieh Liao
  • Publication number: 20070205468
    Abstract: A CMOS integrated circuit includes a substrate having an NMOS region with a P-well and a PMOS region with an N-well. A shallow trench isolation (STI) region is formed between the NMOS and PMOS regions and a composite silicon layer comprising a strained SiGe layer is formed over said P well region and over said N well region. The composite silicon layer is disconnected at the STI region. Gate electrodes are then formed on the composite layer in the NMOS and PMOS regions.
    Type: Application
    Filed: May 9, 2007
    Publication date: September 6, 2007
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yee-Chia Yeo, Chun-Chieh Lin, Fu-Liang Yang, Chen Ming Hu
  • Patent number: 7266119
    Abstract: A NAT system for supporting mobile IP in private networks and its method. A mobile node moves from its home network to a foreign private network and obtains a CoA from the private network. The mobile node sends a registration packet to a home agent in the home network. The registration packet has a swap address option field. A NAT device in the private network swaps the source address with the swap address of the registration packet, and translates the source address into the public address of the NAT device, thereby sending the registration packet to the home agent. After receiving the registration packet, the home agent responds a registration reply packet having a swap address option field filled in the CoA. The NAT device swaps the destination address with the swap address of the registration reply packet, thereby sending the registration reply packet to the mobile node.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: September 4, 2007
    Assignee: Industrial Technology Research Institute
    Inventors: Jung-Hsuan Fan, Chien-Chao Tseng, Chun-Chieh Wang
  • Publication number: 20070195168
    Abstract: A web camera includes an image sensor, which takes an external image; a sensor interface, which is connected to the mage sensor to receive and convert the image taken by the image sensor into digital image data; at least one compression module, which is connected to the sensor interface to receive and compress the digital image data into compressed image data; and a USB interface, which is connected to the compression module to output the compressed image data to a host device having a USB interface port, such as a computer and a USB OTG device, for storage, playing back and other applications.
    Type: Application
    Filed: February 20, 2007
    Publication date: August 23, 2007
    Inventors: Chi-Hsien Wang, Wen-Ming Huang, Wei-Song Yeh, Chun-Chieh Lin, Kuan-Chou Chen
  • Publication number: 20070196382
    Abstract: The present invention provides a biologically pure culture of Saccharomyces cerevisiae strain YA02032 or YA03083, which culture has a characteristic nature capable of producing glutathione and the precursor thereof, ?-glutamylcysteine. A composition comprising the culture and a process for the production of glutathione and/or the precursor thereof, ?-glutamylcysteine, are also provided.
    Type: Application
    Filed: February 22, 2006
    Publication date: August 23, 2007
    Inventors: Jinn-Tsyy Lai, Shin-Ying Lee, Chun-Chieh Hsieh, Chin-Fa Hwang, Chii-Cherng Liao
  • Publication number: 20070176811
    Abstract: An LCD driving circuit and method for increasing effective bit(s) of the source driver is disclosed. A reference voltage generator generates a group of compensated reference voltage levels that are interlaced with original reference voltage level of original reference voltage generator. One of the multiple groups of reference voltage levels is selected by one or more least significant bits (LSBs), and is then inputted to digital-to-Analog converter of the source driver under control of the one or more least significant bits (LSBs), thereby effectively and economically enhancing the gray levels of the display on the LCD panel.
    Type: Application
    Filed: January 27, 2006
    Publication date: August 2, 2007
    Inventors: Chin-Hung Hsu, Ming-Lin Lee, Chun-Chieh Chen, Nan-Ku Lu
  • Publication number: 20070175006
    Abstract: A one-piece elastic clamp device is provided with a pair of gritting members at one end of the main body of the clamp device. A movable axle is provided at the middle of the main body of the clamp device, and a concave portion is provided beneath the movable axle. Two opposite pressing members are respectively formed at the other end of the clamp device, one of the pressing members is provided with an opening in the tail, an elastic sliding piece is provided between the opposite pressing members, one end of the elastic sliding piece is connected with the bottom surface of one of the pressing members, and the other end of the elastic sliding piece is against the inner surface of the other one of the pressing members.
    Type: Application
    Filed: February 1, 2006
    Publication date: August 2, 2007
    Inventor: Chun-Chieh Chen
  • Publication number: 20070164369
    Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.
    Type: Application
    Filed: March 6, 2007
    Publication date: July 19, 2007
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Chao Huang, Yee-Chia Yeo, Chao-Hsiung Wang, Chun-Chieh Lin, Chenming Hu
  • Publication number: 20070164439
    Abstract: A semiconductor interconnect structure having reduced hillock formation and a method for forming the same are provided. The semiconductor interconnect structure includes a conductor formed in a dielectric layer. The conductor includes at least three sub-layers, wherein the ratio of the impurity concentrations in neighboring sub-layers is preferably greater than about two.
    Type: Application
    Filed: January 19, 2006
    Publication date: July 19, 2007
    Inventors: Chung-Hsien Chen, Chun-Chieh Lin, Minghsing Tsai, Shau-Lin Shue
  • Patent number: 7238989
    Abstract: A method of fabricating a CMOS device wherein mobility enhancement of both the NMOS and PMOS elements is realized via strain induced band structure modification, has been developed. The NMOS element is formed featuring a silicon channel region under biaxial strain while the PMOS element is simultaneously formed featuring a SiGe channel region under biaxial compressive strain. A novel process sequence allowing formation of a thicker silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer which is under biaxial tensile strain enhancing electron mobility. The same novel process sequence results in the presence of a thinner silicon layer, overlying the same SiGe layer in the PMOS region, allowing the PMOS channel region to exist in the biaxial compressively strained SiGe layer, resulting in hole mobility enhancement.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: July 3, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yee-Chia Yeo, Chun-Chieh Lin, Fu-Liang Yang, Mong-Song Liang, Chenming Hu
  • Publication number: 20070147197
    Abstract: An objective lens actuating apparatus is provided for an optical read/write head. The apparatus includes a base; a lens holder floating over the base; an objective lens, fixed on the lens holder; two multi-polar magnets mounted on the base; and two coil plates located between the two magnets and fixed on the lens holder. Each coil plate has a tracking coil, a focusing coil, and a tilting coil, which overlaps different magnetic poles of each magnet. The coils generate Lorentz Forces after currents being input into the coils, so as to drive the lens holder moving or tilting.
    Type: Application
    Filed: July 26, 2006
    Publication date: June 28, 2007
    Inventors: Chun-Chieh Huang, Yu-Chien Huang, Jau-Jiu Ju, Chau-Yuan Ke, Chih-Cheng Wu, Tai-Ting Huang
  • Patent number: 7235838
    Abstract: A method for forming a semiconductor device including a DRAM cell structure comprising a silicon on insulator (SOI) substrate with an embedded capacitor structure including providing a substrate comprising an overlying first electrically insulating layer; forming a first electrically conductive layer on the first electrically insulating layer to form a first electrode; forming a capacitor dielectric layer on the first electrode; forming a second electrically conductive layer on the capacitor dielectric layer to form a second electrode; forming a second electrically insulating layer on the second electrode; and, forming a monocrystalline silicon layer over the second electrode to form an SOI substrate comprising a first capacitor structure.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: June 26, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh Lin, Wen-Chin Lee
  • Patent number: 7226832
    Abstract: A CMOS integrated circuit includes a substrate having an NMOS region with a P-well and a PMOS region with an N-well. A shallow trench isolation (STI) region is formed between the NMOS and PMOS regions and a composite silicon layer comprising a strained SiGe layer is formed over said P well region and over said N well region. The composite silicon layer is disconnected at the STI region. Gate electrodes are then formed on the composite layer in the NMOS and PMOS regions.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: June 5, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yee-Chia Yeo, Chun-Chieh Lin, Fu-Liang Yang, Chen Ming Hu