Abstract: An NMOS and PMOS device pair having a selected stress level and type exerted on a respective channel region and method for forming the same, the method including providing a semiconductor substrate; forming isolation regions to separate active areas comprising a PMOS device region and an NMOS device region; lithographically patterning the semiconductor substrate and etching respective recessed areas including the respective NMOS and PMOS device regions into the silicon semiconductor substrate to a predetermined depth; backfilling the respective recessed areas with at least one semiconductor alloy; and, forming gate structures and offset spacers over the respective NMOS and PMOS device regions.

Abstract: A non-volatile memory device with wireless control function which can be divided into two parts comprising a main part and a remote control part. The main part includes a connection port, a memory system and a remote control signal reception module, while the remote control part including a function-key module, a controller, a remote control signal emission module and a power storage unit. The function-key module produces a set of key signals while being pressed, and the controller produces a control signal corresponding to the set of key signals. The remote control signal emission module emits a remote control signal corresponding to the control signal. The remote control signal reception module produces a host control signal corresponding to the remote control signal, and the host control signal is transferred to the host via the connection port to control operations of the host. The power storage unit stores power which is provided to the remote control part while the remote control part is being used.

Abstract: A method is described for forming three or more spacer widths in transistor regions on a substrate. In one embodiment, different silicon nitride thicknesses are formed above gate electrodes followed by nitride etching to form spacers. Optionally, different gate electrode thicknesses may be fabricated and a conformal oxide layer is deposited which is subsequently etched to form different oxide spacer widths. A third embodiment involves a combination of different gate electrode thickness and different nitride thicknesses. A fourth embodiment involves selectively thinning an oxide layer over certain gate electrodes before etching to form spacers. Therefore, spacer widths can be independently optimized for different transistor regions on a substrate to enable better drive current in transistors with narrow spacers and improved SCE control in neighboring transistors with wider spacers. Better drive current is also obtained in transistors with shorter polysilicon thickness.

Abstract: An integrated circuit includes a substrate, a first transistor, and a second transistor. The first transistor has a first gate dielectric portion located between a first gate electrode and the substrate. The first gate dielectric portion includes a first high-permittivity dielectric material and/or a second high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. The second transistor has a second gate dielectric portion located between a second gate electrode and the substrate. The second gate dielectric portion includes the first high-permittivity dielectric material and/or the second high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness may be different than the first equivalent silicon oxide thickness.

Abstract: An information product with a rotational mechanism is provided. The information product comprises a product body, an interface connection port, and a rotational mechanism. The product body further comprises an indentation, which is used to accommodate a plug-in peripheral device. The interface connection port is disposed in the indentation of the product body and is electrically connected with the plug-in peripheral device. The rotational mechanism is disposed in the indentation of the product body and is electrically connected with the product body and the interface connection port, respectively. Wherein, the rotational mechanism is used to adjust the relative position between the interface connection port and the product body, such that the plug-in peripheral device electrically connected with the interface connection port can be accommodated in the indentation with the help of the rotational mechanism.

Abstract: A method of forming a copper filled semiconductor feature having improved bulk properties including providing a semiconductor process wafer having a process surface including an opening for forming a semiconductor feature; depositing at least one metal dopant containing layer over the opening to form a thermally diffusive relationship to a subsequently deposited copper layer; depositing said copper layer to substantially fill the opening; and, thermally treating the semiconductor process wafer for a time period sufficient to distribute at least a portion of the metal dopants to collect along at least a portion of the periphery of said copper layer including a portion of said copper layer grain boundaries.

Abstract: Disclosed herein is a magnetoresistive structure having a non-planar form. Embodiments of the present MR structure includes those having at least one inflection between a first portion of the MR structure that is somewhat vertical relative to a substrate and a second portion of the MR structure that is somewhat horizontal relative to the substrate. Such a structure can be used for memory device, for example an MRAM memory device, wherein the memory density is increased compared to devices having prior planar MR structures without reducing the surface area of the MR structures.

Abstract: A transistor structure comprises a channel region overlying a substrate region. The substrate region comprises a first semiconductor material with a first lattice constant. The channel region comprises a second semiconductor material with a second lattice constant. The source and drain regions are oppositely adjacent the channel region and the top portion of the source and drain regions comprise the first semiconductor material. A gate dielectric layer overlies the channel region and a gate electrode overlies the gate dielectric layer.

Abstract: A terminal structure of a socket has two abutting contact surfaces on a terminal to form an acute angle to become a guiding mechanism to couple and contact with a pin of a chip easier and more accurately, and reduce faulty coupling of the pin and prevent the pin and terminal from deformation, fracturing or defective contact caused by tilting of the pin during insertion. The terminal structure of a socket may be applied on SMT and DIP applications, and is adaptable to pin slots of various shapes, and provide improved common sharing capability and applicability, and may be fabricated at a lower cost.

Abstract: An anti-vibration system for an electronic device. A sensor detects vibration of the electronic device and converts the vibration to an electrical signal, and a controller connected to the sensor receives the electrical signal and transmits a control signal. An anti-vibration device is connected to the controller and activated by the control signal to cancel the vibration.

Abstract: Maintaining photoresist thickness and uniformity over a substrate that includes various cavities presents problems, such as preventing distortion of features in the resist image close to cavity edges. These problems have been overcome by laying down the photoresist as two separate layers. The first layer is used to eliminate or reduce problems associated with the presence of the cavities. The second layer is processed in the normal way and does not introduce distortions close to a cavity's edge. A first embodiment introduces some liquid into the cavity before laying down the first layer while the second embodiment etches away part of the first layer before applying the second one. Application of the process to the formation of a cantilever that overhangs a cavity is also described.

Abstract: A high-speed, low-noise charge pump for use in a phase-locked loop. The charge pump is constituted by first and second cascode current mirrors, as well as first and second switching transistors. The first cascode current mirror includes a first output mirror transistor and a first output cascode transistor. The first switching transistor is interposed between the first output mirror and the first output cascode transistors. During assertion of a first control signal, the first switching transistor is turned on so a first mirror current can flow through an output node. Likewise, the second cascode current mirror includes a second output mirror transistor and a second output cascode transistor. The second switching transistor is interposed between the second output mirror and the second output cascode transistors. During assertion of a second control signal, the second switching transistor is turned on so the second mirror current can flow through the output node.

Abstract: A frequency divider for dividing a frequency of a clock signal by an odd divisor includes a flip-flop chain for latching signals having a number of flip-flops equal to the divisor. The frequency divider also has an XOR gate having two input nodes and an output node, one input node being electrically connected to the clock signal, the other input node being electrically connected to an inverted output node of the last flip-flop, and the output node of the XOR gate being electrically connected to clock input nodes of the odd flip-flops in the flip-flop chain. The frequency divider further has an inverter, an input node of the inverter being electrically connected to the output node of the XOR gate, an output node of the inverter being electrically connected to clock input nodes of the even flip-flops in the flip-flop chain.

Abstract: A CMOS integrated circuit includes a substrate having an NMOS region with a P-well and a PMOS region with an N-well. A shallow trench isolation (STI) region is formed between the NMOS and PMOS regions and a composite silicon layer comprising a strained SiGe layer is formed over said P well region and over said N well region. The composite silicon layer is disconnected at the STI region. Gate electrodes are then formed on the composite layer in the NMOS and PMOS regions.

Abstract: Abstract of the Disclosure A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portion reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.

Abstract: An optical head to access data on an optical recording medium, which has two data storage densities, includes two sets of optical path systems to provide two optical paths that are crossed. Each optical path system includes a laser light generation unit, a light guiding unit, a converging objective lens and a photo detector. The light guiding unit is located on the optical path of the laser light generation unit, to direct the laser light to pass through the converging objective lens and focus on the data side of the optical recording medium to carry optical data signals from the data side. The laser light returns to the light guiding unit and travels along the optical path and is received by the photo detector.

Abstract: A method for forming a semiconductor device including a DRAM cell structure comprising a silicon on insulator (SOI) substrate with an embedded capacitor structure including providing a substrate comprising an overlying first electrically insulating layer; forming a first electrically conductive layer on the first electrically insulating layer to form a first electrode; forming a capacitor dielectric layer on the first electrode; forming a second electrically conductive layer on the capacitor dielectric layer to form a second electrode; forming a second electrically insulating layer on the second electrode; and, forming a monocrystalline silicon layer over the second electrode to form an SOI substrate comprising a first capacitor structure.

Abstract: A delay locked loop clock generation circuit (100) includes a delay locked loop circuit (18), a dummy delay line (40), and a watch dog circuit (32). The delay locked loop circuit includes a delay line (20), a phase detector (25), and a charge pump circuit (30) having an input connected to the output (27) of the phase detector and an output (23) producing a delay control signal (Vctrl) coupled to the stages of the delay line of the delay locked loop circuit. The stages of the delay line are precisely matched to those of the dummy delay line (40). Tap points of the dummy delay line are connected to inputs of the watchdog circuit (32), which operates to generate control signals (34A,B) applied to control the phase detector (25 and the charge pump circuit (30). Tap point signals of the delay line (20) are decoded to produce clock signals (52) for a pipeline ADC (54).

Abstract: A method of fabricating a CMOS device wherein mobility enhancement of both the NMOS and PMOS elements is realized via strain induced band structure modification, has been developed. The NMOS element is formed featuring a silicon channel region under biaxial strain while the PMOS element is simultaneously formed featuring a SiGe channel region under biaxial compressive strain. A novel process sequence allowing formation of a thicker silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer which is under biaxial tensile strain enhancing electron mobility. The same novel process sequence results in the presence of a thinner silicon layer, overlying the same SiGe layer in the PMOS region, allowing the PMOS channel region to exist in the biaxial compressively strained SiGe layer, resulting in hole mobility enhancement.

Abstract: A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.