Patents by Inventor Chun Chieh

Chun Chieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070124492
    Abstract: The present invention provides a PoC system (push-to-talk over cellular system) and a method for distributing media data in PoC. The PoC system includes a plurality of clients, a controlling server and a first participating server. In the present invention, since a media receiving port is established in the first participating server which manages at least two clients at the same time, and when a media data is going to be distributed to the clients managed by the first participating server, the controlling server delivers the media data to the media receiving port only. In addition, a multicast addressing technology is further used in the first participating server, therefore, the path of delivering media data is changed and the efficiency of media data delivery during a communication is improved.
    Type: Application
    Filed: January 2, 2006
    Publication date: May 31, 2007
    Inventors: Yien-Chang Liao, Fang-Ming Lai, Mu-Liang Wang, Chun-Chieh Wang
  • Publication number: 20070118237
    Abstract: An autocontrol method is provided for creating a simulated model that represents an autocontrol system. The autocontrol system includes a controller, a sensor and a plant. The simulated model includes a simulated controller, a simulated sensor, and a simulated plant corresponding to the controller, the sensor, and the plant respectively. The autocontrol simulating method includes steps of: loading parameter values of the controller and the sensor, the parameter values of the controller and the sensor being used as values for the simulated controller and the simulated sensor; setting parameter values of the simulated plant; calculating values for characteristic indicators of the simulated model; and depicting characteristic curves of the simulated model based on the values for characteristic indicators. A related autocontrol method for implementing the autocontrol method is also disclosed.
    Type: Application
    Filed: June 27, 2006
    Publication date: May 24, 2007
    Inventor: Chun-Chieh Wang
  • Publication number: 20070117358
    Abstract: A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.
    Type: Application
    Filed: January 12, 2007
    Publication date: May 24, 2007
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pang-Yen Tsai, Liang-Gi Yao, Chun-Chieh Lin, Wen-Chin Lee, Shih-Chang Chen
  • Publication number: 20070107287
    Abstract: An information display folder is provided herein.
    Type: Application
    Filed: August 4, 2006
    Publication date: May 17, 2007
    Inventor: Chun-chieh Huang
  • Patent number: 7207707
    Abstract: The back light module of LCD device of the present invention is to use the two ends of reflecting plate to roll up and cover light generating units and reaching the function of lamp reflector. Also, the problem of EMI (electric magnetic interference) can be overcome by covering a shell with an EMI protection function on the roll up ends and/or coating or covering the metal with an EMI protection function on one surface of the reflecting plate.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: April 24, 2007
    Assignee: AU Optronics Corporation
    Inventors: Hsin-Tao Huang, Chun-Chieh Chu
  • Publication number: 20070085210
    Abstract: An interconnect structure is described, disposed on a substrate with a conductive part thereon and including a first porous low-k layer on the substrate, a damascene structure in the first porous low-k layer electrically connecting with the conductive part, a second porous low-k layer over the first porous low-k layer and the damascene structure, and a UV cutting layer at least between the first and the second porous low-k layers, wherein the UV cutting layer is a UV reflection layer or a UV reflection-absorption layer.
    Type: Application
    Filed: January 26, 2006
    Publication date: April 19, 2007
    Inventors: Feng-Yu Hsu, Chih-Chien Liu, Chun-Chieh Huang, Jei-Ming Chen, Shu-Jen Sung
  • Patent number: 7206930
    Abstract: A method is provided to reduce strapping devices in a computer system having at least one configurable device, which includes the following steps. A configuration value stored in a non-volatile memory is first provided. During power-up and reset of the computer system, a processor reset signal and a bus reset signal of a high-speed peripheral bus are both asserted, wherein the high-speed peripheral bus is included in the computer system. When an operation clock of the high-speed peripheral bus reaches its working voltage and frequency, the configuration value is fetched from the non-volatile memory. The fetching step is repeated until a most significant bit (MSB) of a fetched configuration value changes from a first state to a second state.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: April 17, 2007
    Assignee: Silicon Integrated Systems Corp.
    Inventors: Jen-Pin Su, Chun-Chieh Wu, Chao-Yu Chen
  • Patent number: 7202122
    Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.
    Type: Grant
    Filed: June 11, 2004
    Date of Patent: April 10, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Chao Huang, Yee-Chia Yeo, Chao-Hsiung Wang, Chun-Chieh Lin, Chenming Hu
  • Publication number: 20070071358
    Abstract: The present image processing apparatus includes a pixel arrangement controller and two data unit buffers coupled with the pixel arrangement controller. This controller can rearrange the addresses of the pixels in the corresponding data unit buffer according to the size of the block. Accordingly, the pixel data of the same block can be arranged in sequential addresses of the data unit buffer. Therefore, the pixel data may be processed as a batch.
    Type: Application
    Filed: September 19, 2006
    Publication date: March 29, 2007
    Applicant: ATEN INTERNATIONAL CO., LTD.
    Inventors: Kai-Cheng Chan, Chun-Chieh Chen
  • Publication number: 20070073496
    Abstract: A detection functionality of any type sensor is integrated into a flash memory disk. The sensor detects its environment and generates signals constantly. A microcontroller, connected with the sensor, saves all signals into a flash memory. A connection port, connected with the microcontroller, enables the flash memory disk to transfer its data to and from a computer when the connection port is coupled with the computer. A battery supplies power to the flash memory, the sensor and the microcontroller.
    Type: Application
    Filed: September 29, 2005
    Publication date: March 29, 2007
    Applicant: Ritek Corporation
    Inventors: Yu-Chuan Lin, Chun-Chieh Chen, Chang-Yi Chen
  • Patent number: 7183593
    Abstract: A heterostructure resistor comprises a doped region formed in a portion of a semiconductor substrate, the substrate comprising a first semiconductor material having a first natural lattice constant. The doped region comprises a semiconductor layer overlying the semiconductor substrate. The semiconductor layer comprises a second semiconductor material with a second natural lattice constant.
    Type: Grant
    Filed: December 24, 2003
    Date of Patent: February 27, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yee-Chia Yeo, Wen-Chin Lee, Chih-Hsin Ko, Chung-Hu Ge, Chun-Chieh Lin, Chenming Hu
  • Patent number: 7175709
    Abstract: A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.
    Type: Grant
    Filed: May 17, 2004
    Date of Patent: February 13, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pang-Yen Tsai, Liang-Gi Yao, Chun-Chieh Lin, Wen-Chin Lee, Shih-Chang Chen
  • Publication number: 20070032252
    Abstract: A method for remote controlling a wireless communication device by a message includes the following steps: the wireless communication device receives a message; and the wireless communication device executes a corresponding operation according to the data stored in the TP-User-Data (TP-UD) field or the data stored in the TP-Protocol-Identifier (TP-PID) field. A user can control the wireless communication device to perform functions like increasing volume or switching from a silent mode to a sound mode, or even switching the mobile phone off, through transmitting a text message to the mobile phone.
    Type: Application
    Filed: August 2, 2006
    Publication date: February 8, 2007
    Inventor: Chun-Chieh Yang
  • Patent number: 7172933
    Abstract: A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portions reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: February 6, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chun Huang, Bow-Wen Chan, Baw-Ching Perng, Lawrence Sheu, Hun-Jan Tao, Chih-Hsin Ko, Chun-Chieh Lin
  • Publication number: 20070019251
    Abstract: A double-side image scanning method and device is provided, wherein the scanning device includes a scanning module and a processing unit. The double-side image scanning method is used to determine the image range of the first side of the document through processing a first image signal obtained by scanning the first side of a document, and use the image range thus obtained as the image range of the second side, thus achieving the objective of automatically determining the size of the document to be scanned and the scanning position, and scanning the double sides of a document speedily.
    Type: Application
    Filed: July 14, 2006
    Publication date: January 25, 2007
    Applicant: Avision Inc.
    Inventor: Chun-Chieh Liao
  • Patent number: 7161204
    Abstract: A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.
    Type: Grant
    Filed: April 4, 2005
    Date of Patent: January 9, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Lin, Lan-Lin Chao, Chia-Shiung Tsai, Fu-Liang Yang, Chia-Hui Lin, Chanming Hu
  • Publication number: 20060286740
    Abstract: Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide and the second silicide may be an alloy silicide.
    Type: Application
    Filed: August 29, 2006
    Publication date: December 21, 2006
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Chieh LIN, Wen-Chin Lee, Yee-Chia Yeo, Chuan-Yi Lin, Chenming Hu
  • Patent number: D534501
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: January 2, 2007
    Inventor: Chun-Chieh Yao
  • Patent number: D543966
    Type: Grant
    Filed: July 7, 2006
    Date of Patent: June 5, 2007
    Assignee: Quanta Computer Inc.
    Inventors: Chun-Chieh Peng, Chi-Jen Yao
  • Patent number: D543967
    Type: Grant
    Filed: April 18, 2006
    Date of Patent: June 5, 2007
    Assignee: Quanta Computer Inc.
    Inventor: Chun-Chieh Peng