Abstract: A vibration absorber system is attached to one side of a chassis of a traverse module of an optical recording/reproducing apparatus. The vibration absorber system includes a vibration absorber for soaking up vibration generated in the optical recording/reproducing apparatus, and at least two elastic dampers for elastically attaching the vibration absorber to the traverse module. Thus, internal vibration is soaked up by the vibration absorber system. Further, the vibration absorber system may be attached to a lighter side of the chassis. Thus, imbalance of the traverse module is reduced or eliminated by the vibration absorber system.

Abstract: A microelectronic device including an insulator located over a substrate, a semiconductor feature and a contact layer. The semiconductor feature has a thickness over the insulator, a first surface opposite the insulator, and a sidewall spanning at least a portion of the thickness. The contact layer has a first member extending over at least a portion of the first surface and a second member spanning at least a portion of the sidewall.

Abstract: The present invention discloses a multi-scraper structure. A plurality of scrapers is used in a cleaning panel process for repeatedly scraping the remnant contaminants on the surface of the panel. Moreover, a pressure control unit is used for immediately modifying the output pressure applied to a second scraper according to the resistance encountered by a first scraper.

Abstract: The present invention discloses a multi-scraper structure. A plurality of scrapers is used in a cleaning panel process for repeatedly scraping the remnant contaminants on the surface of the panel. Moreover, a pressure control unit is used for immediately modifying the output pressure applied to a second scraper according to the resistance encountered by a first scraper.

Abstract: A method of fabricating a CMOS device wherein mobility enhancement of both the NMOS and PMOS elements is realized via strain induced band structure modification, has been developed. The NMOS element is formed featuring a silicon channel region under biaxial strain while the PMOS element is simultaneously formed featuring a SiGe channel region under biaxial compressive strain. A novel process sequence allowing formation of a thicker silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer which is under biaxial tensile stain enhancing electron mobility. The same novel process sequence results in the presence of a thinner silicon layer, overlying the same SiGe layer in the PMOS region, allowing the PMOS channel region to exist in the biaxial compressively strained SiGe layer, resulting in hole mobility enhancement.

Abstract: A magnetic random access memory (MRAM) device including a magnetic tunneling junction (MTJ) stack separated from one or more proximate conductive layers and/or one or more proximate MTJ stacks by a low-k dielectric material.

Abstract: A NAT system for supporting mobile IP in private networks and its method. A mobile node moves from its home network to a foreign private network and obtains a CoA from the private network. The mobile node sends a registration packet to a home agent in the home network. The registration packet has a swap address option field. A NAT device in the private network swaps the source address with the swap address of the registration packet, and translates the source address into the public address of the NAT device, thereby sending the registration packet to the home agent. After receiving the registration packet, the home agent responds a registration reply packet having a swap address option field filled in the CoA. The NAT device swaps the destination address with the swap address of the registration reply packet, thereby sending the registration reply packet to the mobile node.

Abstract: A process for fabricating CMOS devices, featuring a channel region comprised with a strained SiGe layer, has been developed. The process features the selective growth of a composite silicon layer on the top surface of N well and P well regions. The composite silicon layer is comprised of a thin, strained SiGe layer sandwiched between selectively grown, undoped silicon layers. The content of Ge in the SiGe layer, between about 20 to 40 weight percent, allows enhanced carrier mobility to exist without creation of silicon defects. A thin silicon dioxide gate insulator is thermally grown from a top portion of the selectively grown silicon layer, located overlying the selectively grown SiGe layer.

Abstract: A fabrication method and structure for a PBCA, and tool for assembly of the structure. The structure includes a circuit board, at least one first solder joint, a plurality of second solder joints, and an electronic device. The circuit board has a solder mask, having a plurality of openings exposing at least one first pad and a plurality of second pads arranged beyond the first pad, on a surface. The first solder joint has a maximum width J1 and electrically connects to the first pad. The second solder joints respectively have a maximum width J2 exceeding J1 and respectively electrically connect to the second pads. The electronic device has a plurality of third pads, arranged substantially corresponding to the openings, respectively electrically connecting to the first pad and second pads.

Abstract: An optical sub-assembly (OSA) module for suppressing optical back-reflection and effectively guiding light from a light source to an optical waveguide is disclosed. The module comprises a light source for emitting light to said optical waveguide and at least one light transmitting element installed between said light source and said optical waveguide. The at least one light transmitting element is arranged to have a configuration for avoiding light to reflect back to the light source and to cause a light beam from said light source to point to said core of said optical waveguide. Thereby, the working distance is increased, and the assembling process of the OSA module is simplified. This new optical design scheme will greatly improve the optical characteristics of an OSA module, increase the optical transceiver propagation distance, and reduce the difficulty of OSA assembly process.

Abstract: A strained-channel semiconductor structure and method of fabricating the same. The strained-channel semiconductor structure comprises a substrate composed of a first semiconductor material with a first natural lattice constant. A channel region is disposed in the substrate and a gate stack is disposed over the strained channel region A pair of source/drain regions are oppositely disposed in the substrate adjacent to the channel region, wherein each of the source/drain regions comprises a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant rather than the first natural lattice constant, an inner side and an outer side corresponding to the gate stack, and at least one outer sides laterally contacts the first semiconductor material of the substrate.

Abstract: A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.

Abstract: A strained-channel transistor structure with lattice-mismatched zone and fabrication method thereof. The transistor structure includes a substrate having a strained channel region, comprising a first semiconductor material with a first natural lattice constant, in a surface, a gate dielectric layer overlying the strained channel region, a gate electrode overlying the gate dielectric layer, and a source region and drain region oppositely adjacent to the strained channel region, with one or both of the source region and drain region comprising a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant different from the first natural lattice constant.

Abstract: A strained-channel transistor structure with lattice-mismatched zone and fabrication method thereof. The transistor structure includes a substrate having a strained channel region, comprising a first semiconductor material with a first natural lattice constant, in a surface, a gate dielectric layer overlying the strained channel region, a gate electrode overlying the gate dielectric layer, and a source region and drain region oppositely adjacent to the strained channel region, with one or both of the source region and drain region comprising a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant different from the first natural lattice constant.

Abstract: A semiconductor device (100), including a dielectric pedestal (220) located above and integral to a substrate (110) and having first sidewalls (230), a channel region (210) located above the dielectric pedestal (220) and having second sidewalls (240), and source and drain regions (410) opposing the channel region (210) and each substantially spanning one of the second sidewalls (240). An integrated circuit (800) incorporating the semiconductor device (100) is also disclosed, as well as a method of manufacturing the semiconductor device (100).

Abstract: Provided are a semiconductor device and a method for its fabrication. In one example, the semiconductor device includes an active region formed on a substrate using a first silicide type and another active region formed on the substrate using another silicide type. The two silicide types differ and at least one of the two silicides is an alloy silicide. An etch stop layer may overlay at least one of the silicide regions.

Abstract: A semiconductor device having a metal contact is provided. In the preferred embodiment, a metal contact is provided through an interlayer dielectric and is in electrical contact with a metal structure, such as a metal gate electrode of a transistor. A conductive layer is provided between the metal contact and the metal structure. The conductive layer provides one or more of a barrier layer, an adhesion layer, or an etch stop layer. The conductive layer is preferably an elemental metal, metal alloy, metal nitride, metal oxide, or a combination thereof. In an alternative embodiment, the conductive layer is formed of polysilicon.

Abstract: A microelectronic device including an insulator located over a substrate, a semiconductor feature and a contact layer. The semiconductor feature has a thickness over the insulator, a first surface opposite the insulator, and a sidewall spanning at least a portion of the thickness. The contact layer has a first member extending over at least a portion of the first surface and a second member spanning at least a portion of the sidewall.

Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

Abstract: A heterostructure resistor comprises a doped region formed in a portion of a semiconductor substrate, the substrate comprising a first semiconductor material having a first natural lattice constant. The doped region comprises a semiconductor layer overlying the semiconductor substrate. The semiconductor layer comprises a second semiconductor material with a second natural lattice constant.