Abstract: The present invention provides a method and a set of trimming accessories for trimming rubber plate used in an ion implanter. The rubber plate is suitable for use in an ion implanter, wherein the ion implanter has a platform with multiple primary holes and multiple primary notches. In specific embodiments, the set of trimming accessories includes trimming equipment such as a knife or preferably a laser; a template with secondary holes corresponding to primary holes and secondary notches corresponding to primary notches. The template is used as a guide to form a plurality of tertiary holes in the rubber plate corresponding to the plurality of secondary holes of the template and to form a plurality of tertiary notches in the rubber plate corresponding to the plurality of secondary notches of the template.

Abstract: A method and an application installed in a computer system for controlling a plurality of scanners connected to the computer system being capable of feeding documents automatically. The scanners being parallel-connected to the computer system via an interface selecting from a group consisting of IEEE 1394, USB, and SCSI interfaces. The application comprises a scan code for controlling the scanners parallelly and a plurality of image files generated by the scanners scanning documents that can be transferred to the computer system, and a sort code for sorting the images files.

Abstract: A method is provided to reduce strapping devices in a computer system having at least one configurable device, which includes the following steps. A configuration value stored in a non-volatile memory is first provided. During power-up and reset of the computer system, a processor reset signal and a bus reset signal of a high-speed peripheral bus are both asserted, wherein the high-speed peripheral bus is included in the computer system. When an operation clock of the high-speed peripheral bus reaches its working voltage and frequency, the configuration value is fetched from the non-volatile memory. The fetching step is repeated until a most significant bit (MSB) of a fetched configuration value changes from a first state to a second state.

Abstract: A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.

Abstract: A high-speed, low-noise charge pump for use in a phase-locked loop. The charge pump is constituted by first and second cascode current mirrors, as well as first and second switching transistors. The first cascode current mirror includes a first output mirror transistor and a first output cascode transistor. The first switching transistor is interposed between the first output mirror and the first output cascode transistors. During assertion of a first control signal, the first switching transistor is turned on so a first mirror current can flow through an output node. Likewise, the second cascode current mirror includes a second output mirror transistor and a second output cascode transistor. The second switching transistor is interposed between the second output mirror and the second output cascode transistors. During assertion of a second control signal, the second switching transistor is turned on so the second mirror current can flow through the output node.

Abstract: A mobile phone with twin rotational shafts is described. The mobile phone has a front module, a rear module, and a first rotational shaft. The front module further has a display and a second rotational shaft. The rear module further has a set of keys and/or an image sensing unit. The first rotational shaft allows the front module to rotate about 360 degrees on the second module. The second rotational shaft allows the display to rotate about 360 degrees thereon. A rotation direction of the first rotational shaft is about parallel to a picture-taking direction of the image sensing module and perpendicular to a rotation direction of the second rotational shaft. A movement direction of the set of keys is about parallel to the picture-taking direction of the image sensing module.

Abstract: A method is described for forming three or more spacer widths in transistor regions on a substrate. In one embodiment, different silicon nitride thicknesses are formed above gate electrodes followed by nitride etching to form spacers. Optionally, different gate electrode thicknesses may be fabricated and a conformal oxide layer is deposited which is subsequently etched to form different oxide spacer widths. A third embodiment involves a combination of different gate electrode thickness and different nitride thicknesses. A fourth embodiment involves selectively thinning an oxide layer over certain gate electrodes before etching to form spacers. Therefore, spacer widths can be independently optimized for different transistor regions on a substrate to enable better drive current in transistors with narrow spacers and improved SCE control in neighboring transistors with wider spacers. Better drive current is also obtained in transistors with shorter polysilicon thickness.

Abstract: A semiconductor device (100), including a dielectric pedestal (220) located above and integral to a substrate (110) and having first sidewalls (230), a channel region (210) located above the dielectric pedestal (220) and having second sidewalls (240), and source and drain regions (410) opposing the channel region (210) and each substantially spanning one of the second sidewalls (240). An integrated circuit (800) incorporating the semiconductor device (100) is also disclosed, as well as a method of manufacturing the semiconductor device (100).

Abstract: Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide and the second silicide may be an alloy silicide.

Abstract: An integrated circuit includes a substrate, a first transistor, and a second transistor. The first transistor has a first gate dielectric portion located between a first gate electrode and the substrate. The first gate dielectric portion includes a first high-permittivity dielectric material and/or a second high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. The second transistor has a second gate dielectric portion located between a second gate electrode and the substrate. The second gate dielectric portion includes the first high-permittivity dielectric material and/or the second high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness may be different than the first equivalent silicon oxide thickness.

Abstract: A semiconductor chip includes a semiconductor substrate 126, in which first and second active regions are disposed. A resistor 124 is formed in the first active region and the resistor 124 includes a doped region 128 formed between two terminals 136. A strained channel transistor 132 is formed in the second active region. The transistor includes a first and second stressor 141, formed in the substrate oppositely adjacent a strained channel region 143.

Abstract: A semiconductor device or circuit is formed on a semiconductor substrate with first and second semiconductor materials having different lattice-constants. A first transistor includes a channel region formed oppositely adjacent a source and drain region. At least a portion of the source and drain regions are formed in the second semiconductor material thereby forming lattice-mismatched zones in the first transistor. A second component is coupled to the transistor to form a circuit, e.g., an inverter. The second component can be a second transistor having a conductivity type differing from the first transistor or a resistor.

Abstract: An antenna assembly for a wireless communication equipment of the invention comprises a fastening base that is fixedly connected to one side of the wireless communication equipment. An arm, retractable and deployable, has a first end that is movably connected to the fastening base in a manner that the arm, retractable and deployable, is capable of retracting close to the side of the wireless communication equipment and deploying away from the side of the wireless communication equipment. An antenna stem is pivotally connected to a second end of the arm, retractable and deployable. The pivotal connection between the antenna stem and the arm is such that a directional orientation of the antenna stem relative to the axis of the arm is adjustable by rotation for obtaining optimal transmission and reception.

Abstract: A terminal structure of a socket has two abutting contact surfaces on a terminal to form an acute angle to become a guiding mechanism to couple and contact with a pin of a chip easier and more accurately, and reduce faulty coupling of the pin and prevent the pin and terminal from deformation, fracturing or defective contact caused by tilting of the pin during insertion. The terminal structure of a socket may be applied on SMT and DIP applications, and is adaptable to pin slots of various shapes, and provide improved common sharing capability and applicability, and may be fabricated at a lower cost.

Abstract: A method is provided to reduce strapping devices in a computer system having at least one configurable device, which includes the following steps. A configuration value stored in a non-volatile memory is first provided. During power-up and reset of the computer system, a processor reset signal and a bus reset signal of a high-speed peripheral bus are both asserted, wherein the high-speed peripheral bus is included in the computer system. When an operation clock of the high-speed peripheral bus reaches its working voltage and frequency, the configuration value is fetched from the non-volatile memory. The fetching step is repeated until a most significant bit (MSB) of a fetched configuration value changes from a first state to a second state.

Abstract: A process for fabricating CMOS devices, featuring a channel region comprised with a strained SiGe layer, has been developed. The process features the selective growth of a composite silicon layer on the top surface of N well and P well regions. The composite silicon layer is comprised of a thin, strained SiGe layer sandwiched between selectively grown, undoped silicon layers. The content of Ge in the SiGe layer, between about 20 to 40 weight percent, allows enhanced carrier mobility to exist without creation of silicon defects. A thin silicon dioxide gate insulator is thermally grown from a top portion of the selectively grown silicon layer, located overlying the selectively grown SiGe layer.

Abstract: A method for making a SOI wafer with a strained silicon layer for increased electron and hole mobility is achieved. The method forms a porous silicon layer on a seed wafer. A H2 anneal is used to form a smooth surface on the porous silicon. A strain free (relaxed) epitaxial SixGe1-x layer is deposited and a bonding layer is formed. The seed wafer is then bonded to a handle wafer having an insulator on the surface. A spray etch is used to etch the porous Si layer resulting in a SOI handle wafer having portions of the porous Si layer on the relaxed SixGe1-x. The handle wafer is then annealed in H2 to convert the porous Si to a smooth strained Si layer on the relaxed SiGe layer of the SOI wafer.

Abstract: A frequency divider for dividing a frequency of a clock signal by an odd divisor includes a flip-flop chain for latching signals having a number of flip-flops equal to the divisor. The frequency divider also has an XOR gate having two input nodes and an output node, one input node being electrically connected to the clock signal, the other input node being electrically connected to an inverted output node of the last flip-flop, and the output node of the XOR gate being electrically connected to clock input nodes of the odd flip-flops in the flip-flop chain. The frequency divider further has an inverter, an input node of the inverter being electrically connected to the output node of the XOR gate, an output node of the inverter being electrically connected to clock input nodes of the even flip-flops in the flip-flop chain.

Abstract: An information product with a rotational mechanism is provided. The information product comprises a product body, an interface connection port, and a rotational mechanism. The product body further comprises an indentation, which is used to accommodate a plug-in peripheral device. The interface connection port is disposed in the indentation of the product body and is electrically connected with the plug-in peripheral device. The rotational mechanism is disposed in the indentation of the product body and is electrically connected with the product body and the interface connection port, respectively. Wherein, the rotational mechanism is used to adjust the relative position between the interface connection port and the product body, such that the plug-in peripheral device electrically connected with the interface connection port can be accommodated in the indentation with the help of the rotational mechanism.

Abstract: One embodiment is directed to a method for trimming a rubber plate which is configured to be placed on a platform of an ion implanter, wherein the platform of the ion implanter includes a plurality of primary holes and a plurality of primary notches. The method comprises providing a template including a plurality of secondary holes corresponding to the plurality of primary holes of the platform of the ion implanter and a plurality of secondary notches corresponding to the plurality of primary notches of the platform of the ion implanter; and trimming the rubber plate using the template as a guide to form a plurality of tertiary holes in the rubber plate corresponding to the plurality of secondary holes of the template and to form a plurality of tertiary notches in the rubber plate corresponding to the plurality of secondary notches of the template.