Patents by Inventor Chun Chieh

Chun Chieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040090383
    Abstract: An antenna assembly for a wireless communication equipment of the invention comprises a fastening base that is fixedly connected to one side of the wireless communication equipment. An arm, retractable and deployable, has a first end that is movably connected to the fastening base in a manner that the arm, retractable and deployable, is capable of retracting close to the side of the wireless communication equipment and deploying away from the side of the wireless communication equipment. An antenna stem is pivotally connected to a second end of the arm, retractable and deployable. The pivotal connection between the antenna stem and the arm is such that a directional orientation of the antenna stem relative to the axis of the arm is adjustable by rotation for obtaining optimal transmission and reception.
    Type: Application
    Filed: November 12, 2002
    Publication date: May 13, 2004
    Inventors: Chun-Chieh Wang, Shih-Ying Lin
  • Patent number: 6727017
    Abstract: A Li-ion polymer battery and methods for its fabrication. A first and second layer, of a polymer/particulate material composition, separate and bind each anode and cathode. The polymer of the first layer and its associated solvent differ from the polymer of the second layer and its associated solvent. Solubility requirements are such that the polymer of the first layer is non-soluble in the solvent of the second layer, and the polymer of the second layer is non-soluble in the solvent of the first layer. The polymers and particulate materials of the layers form a porous structure for containing the electrolyte of the battery so as to eliminate the need for a substantial case for enclosing the battery.
    Type: Grant
    Filed: April 6, 2001
    Date of Patent: April 27, 2004
    Assignee: Changs Ascending Enterprise Co., Ltd.
    Inventors: Tsun-Yu Chang, Prashant N. Kumta, Chun-Chieh Chang
  • Publication number: 20040077142
    Abstract: Within a method for forming a capacitor within a microelectronic fabrication, there is employed a bilayer capacitor dielectric layer formed in part of an aluminum oxide dielectric material deposited employing an atomic layer deposition (ALD) method, and subsequently plasma treated. The aluminum oxide dielectric material deposited employing the atomic layer deposition (ALD) method and subsequently plasma treated provides for enhanced performance of the capacitor.
    Type: Application
    Filed: October 17, 2002
    Publication date: April 22, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lan-Lin Chao, Chia-Shiung Tsai, Chun Chieh Lin
  • Publication number: 20040066220
    Abstract: A high-speed high-current charge-pump circuit capable of outputting a programmable current range. The charge-pump circuit includes first and second current mirror circuits. The first and the second current mirror circuits produce a first output current from a first supply current and a second output current from a second supply current, respectively, and sources/sinks the first and the second output currents to and from an output node. Also, the charge-pump circuit includes first and second current steering means. The first current steering means directs the first supply current to the first current mirror circuit in response to a first pair of differential signals. On the other hand, the second current steering means directs the second supply current to the second current mirror circuit in response to a second pair of differential signals.
    Type: Application
    Filed: October 3, 2002
    Publication date: April 8, 2004
    Inventor: Chun-Chieh Chen
  • Publication number: 20040053123
    Abstract: A Li-ion polymer battery and methods for its fabrication. A first and second layer, of a polymer/particulate material composition, separate and bind each anode and cathode. The polymer of the first layer and its associated solvent differ from the polymer of the second layer and its associated solvent. Solubility requirements are such that the polymer of the first layer is non-soluble in the solvent of the second layer, and the polymer of the second layer is non-soluble in the solvent of the first layer. The polymers and particulate materials of the layers form a porous structure for containing the electrolyte of the battery so as to eliminate the need for a substantial case for enclosing the battery.
    Type: Application
    Filed: September 17, 2003
    Publication date: March 18, 2004
    Applicant: Changs Ascending Enterprise Co.
    Inventors: Tsun-Yu Chang, Prashant N. Kumta, Chun-Chieh Chang
  • Patent number: 6707748
    Abstract: A back up power embodied non-volatile memory device including a connection port, a power supply unit and a memory system. A host machine provides data and power to the connection port through an external bus. The memory system holds the data received from the connection port temporarily and transfers the data to a non-volatile memory unit inside the memory system. The power supply unit provides necessary power to complete the transfer of temporarily stored data inside the memory system to the non-volatile memory unit to become readable data when host power suddenly fails.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: March 16, 2004
    Assignee: Ritek Corporation
    Inventors: Yu-Chuan Lin, Chun-Chieh Chen, Hung-Ju Shen, Chien-Hua Wu, Sheng-Lin Chiu, Huan-Tung Wang, Hsin-Chih Hung
  • Patent number: 6703271
    Abstract: A process for fabricating CMOS devices, featuring a channel region comprised with a strained SiGe layer, has been developed. The process features the selective growth of a composite silicon layer on the top surface of N well and P well regions. The composite silicon layer is comprised of a thin, strained SiGe layer sandwiched between selectively grown, undoped silicon layers. The content of Ge in the SiGe layer, between about 20 to 40 weight percent, allows enhanced carrier mobility to exist without creation of silicon defects. A thin silicon dioxide gate insulator is thermally grown from a top portion of the selectively grown silicon layer, located overlying the selectively grown SiGe layer.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: March 9, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yee-Chia Yeo, Chun Chieh Lin, Fu-Liang Yang, Chen Ming Hu
  • Patent number: 6704557
    Abstract: An interference protection system includes a receiving section for receiving an electromagnetic signal, a detector for detecting a jamming signal, and a control system for orienting a changeable null direction of an antenna system to reduce interference in a receiver from the jamming signal.
    Type: Grant
    Filed: April 22, 1999
    Date of Patent: March 9, 2004
    Assignee: Lucent Technologies Inc.
    Inventors: Sreenath Krishnamurthy, Chun Chieh Kung, Kun-Yii Tu
  • Patent number: 6696672
    Abstract: A heating lamp bracket for reaction chambers of evaporation coating machines. The heating lamp bracket uses paired and insulation devices to mount heating lamps to a chamber wall of a reaction chamber. The bracket includes a mounting frame that has an insulation outer surface and a mounting outer face opposing to the insulation outer surface. The insulation outer surface has at least one insulation member located thereon for fastening the mounting frame to the chamber wall. The mounting outer surface has at least two independent mounting spots for connecting respectively a connection end of the corresponding heating lamp. The independent mounting spots and non-encased type insulation members of the present invention allows for the replacement of the heating lamps and defective insulation.
    Type: Grant
    Filed: December 31, 2001
    Date of Patent: February 24, 2004
    Assignee: Mosel Vitelic Inc.
    Inventors: Hung-Lin Ke, Hua-Jen Tseng, Chun-Chieh Lee, Muh-Lang Jang
  • Publication number: 20040033632
    Abstract: The present invention provides a method of producing an added defect count for monitoring the property of chambers or wafers. First, a proper pre-process sensitivity is determined with map to map process by maximizing the summation of a mapping rate and a catching rate. Second, a wafer is scanned with the proper pre-process sensitivity and a pre-process particle number P1 is recorded. Third, a manufacturing step is processed on the wafer. Fourth, the wafer is scanned with the most sensitive scale of the post-process sensitivities and a post-process particle number P2 is recorded. Finally, the post-process particle number P2 is subtracted from the pre-process particle number P1.
    Type: Application
    Filed: August 15, 2002
    Publication date: February 19, 2004
    Inventors: Wei-Ming Chen, Kun-Yu Liu, Chun-Chieh Chen, Lien-Che Ho
  • Publication number: 20040015624
    Abstract: A method and an application installed in a computer system for controlling a plurality of scanners connected to the computer system being capable of feeding documents automatically. The scanners being parallel-connected to the computer system via an interface selecting from a group consisting of IEEE 1394, USB, and SCSI interfaces. The application comprises a scan code for controlling the scanners parallelly and a plurality of image files generated by the scanners scanning documents that can be transferred to the computer system, and a sort code for sorting the images files.
    Type: Application
    Filed: September 25, 2002
    Publication date: January 22, 2004
    Inventors: Po-Sheng Shih, Chun-Chieh Liao
  • Patent number: 6656844
    Abstract: A method of forming a DRAM capacitor structure featuring increased surface area, has been developed. The method features a polysilicon top plate structure located overlying an array comprised of individual polysilicon storage node structures. Each polysilicon storage node structure is comprised with tall, vertical features, and additional surface area is obtained via removal of butted insulator layer from a first group of surfaces of the storage node structures. Insulator layer remains butted to a second group of storage node structure surfaces to prevent collapse of the tall, vertical features of the storage node structures during subsequent processing sequences.
    Type: Grant
    Filed: October 18, 2001
    Date of Patent: December 2, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chun-Chieh Lin, Wong-Cheng Shih
  • Publication number: 20030210601
    Abstract: A back up power embodied non-volatile memory device comprising a connection port, a power supply unit and a memory system. A host machine provides data and power to the connection port through an external bus. The memory system holds the data received from the connection port temporarily and transfers the data to a non- volatile memory unit inside the memory system. The power supply unit provides necessary power to complete the transfer of temporarily stored data inside the memory system to the non-volatile memory unit to become readable data when host power suddenly fails.
    Type: Application
    Filed: December 31, 2002
    Publication date: November 13, 2003
    Inventors: YU-CHUAN LIN, CHUN-CHIEH CHEN, HUNG-JU SHEN, CHIEN-HUA WU, SHENG-LIN CHIU, HUAN-TUNG WANG, HSIN-CHIH HUNG
  • Publication number: 20030208574
    Abstract: A method for previewing a MIB (Management Information Base) group table in a SNMP (Simple Network Management Protocol) network device comprises transmitting a packet having preview facility from a NMS (Network Management Station) to the network device; after the network device has received the packet, transmitting items in the MIB group table which supports the SNMP back to the NMS in a reply packet; and enabling the NMS to perform an analysis on the reply packet so as to preview items of the MIB group table in the network device which support SNMP.
    Type: Application
    Filed: December 27, 2001
    Publication date: November 6, 2003
    Inventors: Yung-Hsin Chen, Yu-Min Yan, Ming-Chih Chang, Chun-Chieh Huang
  • Publication number: 20030184611
    Abstract: A microarray printing device includes an elongate holder having a plurality of receiving slots, and printing pins. Each printing pin extends through and is linearly movable in a corresponding receiving slot in the holder, and has head and tip portions. The tip portion has a tapered surface, a tip end face, a plurality of capillary channels that extend axially on the tapered surface from the tip end face, and a plurality of passages formed on the tapered surface for collecting liquid and connected respectively to the channels opposite to the tip end face.
    Type: Application
    Filed: March 27, 2002
    Publication date: October 2, 2003
    Inventors: Hsien-Nan Kuo, Shui-Chi Yen, Chun-Chieh Wang
  • Patent number: 6614708
    Abstract: A non-volatile memory device with a built-in laser indicator. The non-volatile memory device includes a connective port, a buffer, a non-volatile memory unit, a memory controller, a battery and a laser indicator. The connective port connects electrically to a host machine. The host machine transfers data and provides power to the connective port through an external bus. The buffer holds the data transmitted to the connective port temporarily. The memory controller controls the transfer of data from the buffer into the non-volatile memory unit. The battery receives host power and stores up some host power to serve as backup power. The battery also provides the power for driving the laser indicator.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: September 2, 2003
    Assignee: Ritek Corporation
    Inventors: Yu-Chuan Lin, Chun-Chieh Chen, Hung-Ju Shen, Tao-Chien Wei, Chien-Hua Wu, Sheng-Lin Chiu, Huan-Tung Wang, Hsin-Chih Hung
  • Publication number: 20030162348
    Abstract: A process for fabricating CMOS devices, featuring a channel region comprised with a strained SiGe layer, has been developed. The process features the selective growth of a composite silicon layer on the top surface of N well and P well regions. The composite silicon layer is comprised of a thin, strained SiGe layer sandwiched between selectively grown, undoped silicon layers. The content of Ge in the SiGe layer, between about 20 to 40 weight percent, allows enhanced carrier mobility to exist without creation of silicon defects. A thin silicon dioxide gate insulator is thermally grown from a top portion of the selectively grown silicon layer, located overlying the selectively grown SiGe layer.
    Type: Application
    Filed: November 30, 2001
    Publication date: August 28, 2003
    Applicant: Taiwan Semiconductor Manufacturing Company
    Inventors: Yee-Chia Yeo, Chun Chieh Lin, Fu-Liang Yang, Chen Ming Hu
  • Patent number: D487734
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: March 23, 2004
    Assignee: Quanta Computer Inc.
    Inventors: Chun-Chieh Peng, Gwo-Chyuan Chen
  • Patent number: D488143
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: April 6, 2004
    Assignee: Quanta Computer Inc.
    Inventors: Chih-Kang Ting, Chun-Chieh Peng, Gwo-Chyuan Chen
  • Patent number: D488790
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: April 20, 2004
    Assignee: Quanta Computer, Inc.
    Inventors: Chun-Chieh Peng, Gwo-Chyuan Chen