Patents by Inventor Chun Chieh

Chun Chieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6816748
    Abstract: The present invention proposes a smart automatic recording system and method for monitoring wafer fragmentation, which system comprises a plurality of photographing devices, a multiple-image transmitter, a multiple-image receiver, and a PC. The photographing devices are used to monitor the circumstances when wafers are polished. The photographed images are then transferred to the multiple-image receiver by the multiple-image transmitter. After the multiple-image receiver receives the image signals, it merges the images captured at the same time into the same image frame. Next, the multiple-image receiver transfers the image signal to the input terminal of an image-capturing card in the PC. The PC also receives the wafer-entry and wafer-exit signals and the signal of wafer fragmentation transferred from the port of the polishing apparatus. The present invention can be exploited to facilitate judgement, diagnosis, genuine factor verification, or engineering improvement and management for associated technicians.
    Type: Grant
    Filed: October 12, 2000
    Date of Patent: November 9, 2004
    Assignee: Winbond Electronics Corp.
    Inventors: Ting Kuo Chen, Wen Chin Kuo, Yong Sen Liao, Chun Chieh Lin
  • Patent number: 6812116
    Abstract: A method for making a SOI wafer with a strained silicon layer for increased electron and hole mobility is achieved. The method forms a porous silicon layer on a seed wafer. A H2 anneal is used to form a smooth surface on the porous silicon. A strain free (relaxed) epitaxial SixGe1−x layer is deposited and a bonding layer is formed. The seed wafer is then bonded to a handle wafer having an insulator on the surface. A spray etch is used to etch the porous Si layer resulting in a SOI handle wafer having portions of the porous Si layer on the relaxed SixGe1−x. The handle wafer is then annealed in H2 to convert the porous Si to a smooth strained Si layer on the relaxed SiGe layer of the SOI wafer.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: November 2, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Chao Huang, Yee-Chia Yeo, Kuo-Nan Yang, Chun-Chieh Lin, Chenming Hu
  • Publication number: 20040214112
    Abstract: Maintaining photoresist thickness and uniformity over a substrate that includes various cavities presents problems, such as preventing distortion of features in the resist image close to cavity edges. These problems have been overcome by laying down the photoresist as two separate layers. The first layer is used to eliminate or reduce problems associated with the presence of the cavities. The second layer is processed in the normal way and does not introduce distortions close to a cavity's edge. A first embodiment introduces some liquid into the cavity before laying down the first layer while the second embodiment etches away part of the first layer before applying the second one. Application of the process to the formation of a cantilever that overhangs a cavity is also described.
    Type: Application
    Filed: April 23, 2003
    Publication date: October 28, 2004
    Applicant: Taiwan Semicondutor Manufacturing Co.
    Inventors: Su-Jen Cheng, Bor-Ping Jang, Chun-Chieh Wang, Jy-Jie Gau
  • Publication number: 20040203720
    Abstract: The present invention provide a radio communication device having a transmitter for emitting a radio signal to a corresponding receiver comprise an indicating means and a controller; wherein the indicating means for indicating a transmitted RF power strength status of the transmitter; the controller for detecting and outputting the transmitted power strength status to the indicating means, the controller including a power detecting means; wherein the power detecting means coupled to the transmitter for detecting a transmitted power level of the radio signal emitted from a transmitter to a corresponding receiver.
    Type: Application
    Filed: August 20, 2002
    Publication date: October 14, 2004
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Did-Min Shih, Chun-Chieh Chen, Jyhfong Lin, Peir-Weir Chen
  • Publication number: 20040185613
    Abstract: A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.
    Type: Application
    Filed: March 17, 2004
    Publication date: September 23, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co.
    Inventors: Chun-Chieh Lin, Lan-Lin Chao, Chia-Hui Lin, Fu-Liang Yang, Chia-Shiung Tsai, Chanming Hu
  • Publication number: 20040183691
    Abstract: A non-volatile memory device with wireless control function which can be divided into two parts comprising a main part and a remote control part. The main part includes a connection port, a memory system and a remote control signal reception module, while the remote control part including a function-key module, a controller, a remote control signal emission module and a power storage unit. The function-key module produces a set of key signals while being pressed, and the controller produces a control signal corresponding to the set of key signals. The remote control signal emission module emits a remote control signal corresponding to the control signal. The remote control signal reception module produces a host control signal corresponding to the remote control signal, and the host control signal is transferred to the host via the connection port to control operations of the host. The power storage unit stores power which is provided to the remote control part while the remote control part is being used.
    Type: Application
    Filed: July 11, 2003
    Publication date: September 23, 2004
    Inventors: Yu-Chuan Lin, Chun-Chieh Chen, Hung-Ju Shen, Chien-Hua Wu, Sheng-Lin Chiu, Huan-Tung Wang, Hsin-Chih Hung
  • Patent number: 6794203
    Abstract: The present invention provides a method of producing an added defect count for monitoring the property of chambers or wafers. First, a proper pre-process sensitivity is determined with map to map process by maximizing the summation of a mapping rate and a catching rate. Second, a wafer is scanned with the proper pre-process sensitivity and a pre-process particle number P1 is recorded. Third, a manufacturing step is processed on the wafer. Fourth, the wafer is scanned with the most sensitive scale of the post-process sensitivities and a post-process particle number P2 is recorded. Finally, the post-process particle number P2 is subtracted from the pre-process particle number P1.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: September 21, 2004
    Assignee: Macronix International Co., Ltd.
    Inventors: Wei-Ming Chen, Kun-Yu Liu, Chun-Chieh Chen, Lien-Che Ho
  • Publication number: 20040181627
    Abstract: A device and method for recording the block status information of a nonvolatile memory is disclosed. An interface unit is used to host the nonvolatile memory so that a processor connected to the interface unit can detect the block status information of the nonvolatile memory through the interface unit to obtain a valid or invalid block address. Then, the valid or invalid block address is temporarily stored in a memory unit until all of the blocks are detected by means of the processor. Finally, the valid or invalid block address temporarily stored in the memory unit is written into the nonvolatile memory.
    Type: Application
    Filed: November 25, 2003
    Publication date: September 16, 2004
    Applicant: RiTek Corporation
    Inventors: Yu-Chuan Lin, Chun-Chieh Chen, Sheng-Lin Chiu
  • Publication number: 20040173815
    Abstract: A strained-channel transistor structure with lattice-mismatched zone and fabrication method thereof. The transistor structure includes a substrate having a strained channel region, comprising a first semiconductor material with a first natural lattice constant, in a surface, a gate dielectric layer overlying the strained channel region, a gate electrode overlying the gate dielectric layer, and a source region and drain region oppositely adjacent to the strained channel region, with one or both of the source region and drain region comprising a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant different from the first natural lattice constant.
    Type: Application
    Filed: March 4, 2003
    Publication date: September 9, 2004
    Inventors: Yee-Chia Yeo, Chun-Chieh Lin, Wen-Chin Lee, Chenming Hu
  • Publication number: 20040175872
    Abstract: A method of fabricating a CMOS device wherein mobility enhancement of both the NMOS and PMOS elements is realized via strain induced band structure modification, has been developed. The NMOS element is formed featuring a silicon channel region under biaxial strain while the PMOS element is simultaneously formed featuring a SiGe channel region under biaxial compressive strain. A novel process sequence allowing formation of a thicker silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer which is under biaxial tensile stain enhancing electron mobility. The same novel process sequence results in the presence of a thinner silicon layer, overlying the same SiGe layer in the PMOS region, allowing the PMOS channel region to exist in the biaxial compressively strained SiGe layer, resulting in hole mobility enhancement.
    Type: Application
    Filed: March 7, 2003
    Publication date: September 9, 2004
    Applicant: Taiwan Semiconductor Manufacturing Company
    Inventors: Yee-Chia Yeo, Chun-Chieh Lin, Fu-Liang Yang, Mong-Song Liang, Chenming Hu
  • Publication number: 20040160545
    Abstract: A screen structure capable of embedding a liquid crystal display therein is proposed, wherein a placement hole for disposing a liquid crystal display is provided in a screen partition. Fixing holes for fixing the liquid crystal display are disposed in a movable baffle. Moreover, adjustment sides are disposed at. edges of two projective faces of the movable baffle, respectively. A user can adjust the liquid crystal display to an angular position more suitable for use through the adjustment sides.
    Type: Application
    Filed: February 13, 2003
    Publication date: August 19, 2004
    Inventor: Chun-Chieh Pai
  • Patent number: 6769760
    Abstract: A microarray printing device includes an elongate holder with a plurality of receiving slots and a plurality of printing pins. Each of the printing pins extends through and is linearly movable in a respective one of the slots in the holder, and has head, tip, and shank portions. The shank portion has a surface formed with at least one longitudinal flute extending from the head portion to the tip portion.
    Type: Grant
    Filed: March 19, 2002
    Date of Patent: August 3, 2004
    Assignee: Metal Industries Research and Development Centre
    Inventors: Hsien-Nan Kuo, Chi-Wah Keong, Chun-Chieh Wang, Paul C. K. Chung
  • Patent number: 6764866
    Abstract: Each of a system for qualifying a multiple die under test head and a system for qualifying the multiple die under test head employ selection of a sub-set of die arrays within a calibration standard substrate. The sub-set of die arrays is selected such as to: (1) not overlap in position within the calibration standard substrate; and (2) have in an aggregate no greater than one defective die within each of a series of die locations. The system and the method provide for accurate and efficient qualification of the multiple die under test head and thus accurate and efficient electrical test measurement of a microelectronic product.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: July 20, 2004
    Assignee: Taiwan SEmiconductor Manufacturing Co., Ltd.
    Inventors: Lee-Chung Lin, Jun-Hao Huang, Chun-Chieh Hsiao
  • Publication number: 20040136650
    Abstract: An optical sub-assembly (OSA) module for suppressing optical back-reflection and effectively guiding light from a light source to an optical waveguide is disclosed. The module comprises a light source for emitting light to said optical waveguide and at least one light transmitting element installed between said light source and said optical waveguide. The at least one light transmitting element is arranged to have a configuration for avoiding light to reflect back to the light source and to cause a light beam from said light source to point to said core of said optical waveguide. Thereby, the working distance is increased, and the assembling process of the OSA module is simplified. This new optical design scheme will greatly improve the optical characteristics of an OSA module, increase the optical transceiver propagation distance, and reduce the difficulty of OSA assembly process.
    Type: Application
    Filed: January 10, 2003
    Publication date: July 15, 2004
    Inventors: Wen-Tzung Chen, Chien-Cheng Yang, Chun-Chieh Chang, Chun-Te Lee, Chih-Hsien Chang, Cheng-Ta Chen, Bao-Jen Pong
  • Publication number: 20040121795
    Abstract: A radio communication system for communication between a first mobile system and a second mobile system. Each mobile system has a transceiver for receiving and emitting radio signal. The second mobile system comprises a received signal strength detecting device, a power controller and an indicating device. The received signal strength detecting device detects a received signal strength of the transceiver in the second mobile system. The power controller outputs a transmitted power strength status and controls transmitted power of the transceiver according to the received signal strength. The indicating device receives the transmitted power strength status and indicates a transmitted RF power strength status of the transceiver in the second mobile.
    Type: Application
    Filed: December 4, 2003
    Publication date: June 24, 2004
    Inventors: Did-Min Shih, Chun-Chieh Chen, Bing-Ming Ho
  • Publication number: 20040115900
    Abstract: A method for making a SOI wafer with a strained silicon layer for increased electron and hole mobility is achieved. The method forms a porous silicon layer on a seed wafer. A H2 anneal is used to form a smooth surface on the porous silicon. A strain free (relaxed) epitaxial SixGe1-x layer is deposited and a bonding layer is formed. The seed wafer is then bonded to a handle wafer having an insulator on the surface. A spray etch is used to etch the porous Si layer resulting in a SOI handle wafer having portions of the porous Si layer on the relaxed SixGe1-x. The handle wafer is then annealed in H2 to convert the porous Si to a smooth strained Si layer on the relaxed SiGe layer of the SOI wafer.
    Type: Application
    Filed: December 13, 2002
    Publication date: June 17, 2004
    Applicant: Taiwan Semiconductor Manufacturing Company
    Inventors: Chien-Chao Huang, Yee-Chia Yeo, Kuo-Nan Yang, Chun-Chieh Lin, Chenming Hu
  • Publication number: 20040105329
    Abstract: An interface apparatus having a rotational mechanism for connecting with an interface port in an electronic product is provided. The interface apparatus comprises a body, a connector and a rotational mechanism. The connector is used for connecting with the interface port of an electronic device. The rotational mechanism links up the body with the connector. The rotational mechanism has one to five degrees of freedom of movements. One or a multiple of rotational junctions together provides the degrees of freedom of movements in the rotational mechanism.
    Type: Application
    Filed: September 17, 2003
    Publication date: June 3, 2004
    Inventors: Yu-Chuan Lin, Chun-Chieh Chen, Hung-Ju Shen, Chien-Hua Wu, Sheng-Lin Chiu, Huan-Tung Wang, Hsin-Chih Hung
  • Patent number: D496920
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: October 5, 2004
    Assignee: Quanta Computer, Inc.
    Inventors: Chun-Chieh Peng, Feng-Chun Wang
  • Patent number: D497891
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: November 2, 2004
    Assignee: Quanta Computer, Inc.
    Inventors: Chun-Chieh Peng, Pu-Ching Chuang
  • Patent number: D497892
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: November 2, 2004
    Assignee: Quanta Computer, Inc.
    Inventor: Chun-Chieh Peng