Patents by Inventor Chun Chieh

Chun Chieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11681118
    Abstract: An optical element driving mechanism having an optical axis includes a fixed portion, a movable portion, and a driving assembly. The movable portion is connected to the fixed portion. The driving assembly drives the movable portion to move in a direction that is parallel to the optical axis relative to the fixed portion, when viewed in the direction that is parallel to the optical axis, the optical element driving mechanism is a rectangular structure with a first side, a second side, a third side, and a fourth side, the first side and the third side are opposite, and the first side is adjacent to the second side and the fourth side.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: June 20, 2023
    Assignee: TDK TAIWAN CORP.
    Inventors: Wei-Jhe Shen, Kun-Shih Lin, Yung-Ping Yang, Chun-Chieh Chang, Sheng-Chang Lin, Che-Hsiang Chiu
  • Patent number: 11683888
    Abstract: A package circuit structure includes a multilayer circuit board, an electronic component, and an insulating layer. The multilayer circuit board includes a metal portion and an opening. The opening is extending from a first side of the multilayer circuit board toward the second side of the multilayer circuit board facing the first side. A bottom of the opening is sealed by the metal portion. The electronic component is received in the opening and adhered to the metal portion. The electronic component is electrically connected to the multilayer circuit board and encapsulated in the opening by the insulating layer. A method for manufacturing the package circuit structure is also provided.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: June 20, 2023
    Assignees: Leading Interconnect Semiconductor Technology Qinhuangdao Co, Ltd., Qi Ding Technology Qinhuangdao Co, Ltd., Leading Interconnect Semiconductor Technology (ShenZhen) Co, Ltd.
    Inventors: Chun-Chieh Huang, Chin-Ming Liu
  • Patent number: 11682275
    Abstract: An electronic device with an auxiliary lighting function and an operation method thereof are provided. The electronic device includes a first body, a display screen, and a light-emitting module. The first body has a first surface. The first surface includes a screen area and a border area. The border area surrounds the screen area. The display screen is disposed in the screen area of the first body. The light-emitting module is disposed in the border area of the first body. The light-emitting module provides an illumination light in at least one first area of the border area, and provides an indicating light in at least one second area of the border area.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: June 20, 2023
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Po-Yang Chien, Wei-Yi Chang, Chun-Chieh Chen, Chen-Cheng Wang
  • Patent number: 11679469
    Abstract: A chemical mechanical planarization (CMP) tool includes a platen and a polishing pad attached to the platen, where a first surface of the polishing pad facing away from the platen includes a first polishing zone and a second polishing zone, where the first polishing zone is a circular region at a center of the first surface of the polishing pad, and the second polishing zone is an annular region around the first polishing zone, where the first polishing zone and the second polishing zone have different surface properties.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: June 20, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Michael Yen, Kao-Feng Liao, Hsin-Ying Ho, Chun-Wen Hsiao, Sheng-Chao Chuang, Ting-Hsun Chang, Fu-Ming Huang, Chun-Chieh Lin, Peng-Chung Jangjian, Ji James Cui, Liang-Guang Chen, Chih Hung Chen, Kei-Wei Chen
  • Publication number: 20230188075
    Abstract: A voltage measurement device for pulse-width modulation (PWM) signals is provided, which includes a conversion circuit and a processing circuit. The conversion circuit receives a first PWM signal and a second PWM signal from a motor driving device, and converts the first PWM signal and the second PWM signal into the absolute value signal and the polarity signal of the line-to-line voltage signal between the first PWM signal and the second PWM signal. The processing circuit converts the polarity signal and the absolute value signal into a first integral signal and a second integral signal, and reconstructs the line-to-line voltage signal according to the first integral signal and the second integral signal so as to obtain the reconstructed voltage signal of the line-to-line voltage signal.
    Type: Application
    Filed: December 13, 2021
    Publication date: June 15, 2023
    Inventors: WEN-CHE SHEN, CHENG-MIN CHANG, CHUN-CHIEH CHANG, PO-HUAN CHOU
  • Patent number: 11673223
    Abstract: A chemical mechanical polishing method is provided, including polishing a batch of wafers in sequence on a polishing surface of a polishing pad; conditioning the polishing surface with a pad conditioner, wherein the pad conditioner is operable to apply downward force according to a predetermined downward force stored in a controller to condition the polishing surface; measuring the downward force applied by the pad conditioner with a measurement tool when the pad conditioner is at a home position and after conditioning the polishing surface; comparing the downward force measured by the measurement tool and the predetermined downward force with the controller to determine whether a difference between the downward force measured by the measurement tool and the predetermined downward force exceeds a range of acceptable values; and calibrating the downward force applied by the pad conditioner with the controller when the difference exceeds the range of acceptable values.
    Type: Grant
    Filed: April 1, 2022
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Chen Wei, Jheng-Si Su, Shih-Ho Lin, Jen-Chieh Lai, Chun-Chieh Chan
  • Patent number: 11676898
    Abstract: A method includes forming an insulating layer over a conductive feature; etching the insulating layer to expose a first surface of the conductive feature; covering the first surface of the conductive feature with a sacrificial material, wherein the sidewalls of the insulating layer are free of the sacrificial material; covering the sidewalls of the insulating layer with a barrier material, wherein the first surface of the conductive feature is free of the barrier material, wherein the barrier material includes tantalum nitride (TaN) doped with a transition metal; removing the sacrificial material; and covering the barrier material and the first surface of the conductive feature with a conductive material.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Pang Kuo, Huan-Yu Shih, Wen-Hsuan Chen, Cheng-Lun Tsai, Ya-Lien Lee, Cheng-Hui Weng, Chun-Chieh Lin, Hung-Wen Su, Yao-Min Liu
  • Patent number: 11670541
    Abstract: A first photoresist material is formed. The first photoresist material is exposed through a phase shift mask. The first photoresist material is developed to form a first photoresist layer, wherein the first photoresist layer comprises a plurality of first photoresist patterns and a plurality of first openings between the plurality of first photoresist patterns. A first conductive material is formed in the plurality of first openings. A second photoresist layer is formed over the first conductive material, wherein the second photoresist layer comprises at least one second opening. A second conductive material is formed in the at least one second opening. The first photoresist layer and the second photoresist layer are removed, to form a plurality of first conductive patterns and at least one second conductive pattern. A dielectric layer is formed, wherein the at least one second conductive pattern is disposed in the dielectric layer.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: June 6, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Wang, Hung-Jui Kuo, Jaw-Jung Shin, Ming-Tan Lee
  • Publication number: 20230170406
    Abstract: A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional “2D” semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as “metal fin structure”, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material.
    Type: Application
    Filed: January 26, 2023
    Publication date: June 1, 2023
    Inventors: Chao-Ching CHENG, Hung-Li CHIANG, Chun-Chieh LU, Ming-Yang LI, Tzu- Chiang CHEN
  • Patent number: 11660345
    Abstract: The invention provides a method for enhancing the delivery of an anti-platelet drug for the treatment of acute stroke, comprising delivering a composition comprising an anti-platelet drug and a vehicle that can reduce the binding rate of plasma proteins, so that the anti-platelet drug can achieve the effect of treating acute stroke at a low dose. By use of the neuro-protective efficacy of anti-platelet drug, the invention allows the drug to release slowly to the site of treatment by combining anti-platelet drugs with a vehicle that can reduce the binding rate of plasma proteins to effectively reduce the dose of the anti-platelet drug and consequently reduce the side effects such as hypotension caused by administration of a high dose of the anti-platelet drugs. The invention also provides a pharmaceutical composition for enhancing treatment of acute stroke and a method for treating acute stroke using the pharmaceutical composition of the invention.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: May 30, 2023
    Assignee: REALINN LIFE SCIENCE LIMITED
    Inventors: Jen Cheng Lin, Chun-Chieh Lin, Hsu-Tung Lee, Yu-Ming Fan, Jui-Chi Tsai
  • Patent number: 11663526
    Abstract: A document processing system and method for performing document classification by machine learning include an input module, a processing module, and at least one storage module preconfigured with a classification folder matching a code. Upon completion of a first-instance model construction procedure, the input module receives a document image. The processing module compares the document image with a machine learning model information to generate a computation result and stores the document image in the classification folder according to the computation result. Therefore, classification of the document images is automated according to the code of the corresponding classification folder, thereby enhancing the accuracy and efficiency of document classification.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: May 30, 2023
    Assignee: AVISION INC.
    Inventor: Chun-Chieh Liao
  • Publication number: 20230159596
    Abstract: A Hepatitis E virus (HEV)-based virus like nanoparticle (HEVNP) made with a modified capsid protein containing at least a portion of open reading frame 2 (ORF2) protein conjugated with gold nanocluster is provided. Also provided are methods of targeted delivery of a nucleic acid using the HEVNP.
    Type: Application
    Filed: September 27, 2022
    Publication date: May 25, 2023
    Inventors: R. Holland Cheng, Chun Chieh Chen, Mohammad Ali Baikoghli, Marie Stark
  • Patent number: 11659136
    Abstract: A data conversion device includes a storage circuit and a frequency tuning circuit. The storage circuit is configured to store a pixel data in a high definition multimedia interface (HDMI) signal according to a first clock, and output an image data according to a second clock. The frequency tuning circuit is configured to adjust the second clock according to a control signal and the second clock in the HDMI signal, and transmit the adjusted second clock to the storage circuit.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: May 23, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Che-Wei Yeh, Chien-Hsun Lu, Zhan-Yao Gu, Chun-Chieh Chan
  • Patent number: 11658852
    Abstract: The present invention discloses a signal relay apparatus having frequency calibration mechanism that includes a clock generation circuit, a frequency generation circuit, a clock measuring circuit, a frequency adjusting circuit and a transmission circuit. The clock generation circuit generates a source clock signal. The frequency generation circuit receives the source clock signal and generates a target frequency signal according to a conversion parameter. The clock measuring circuit measures a first frequency offset of a source frequency relative to a first predetermined frequency according to an external reference clock signal. The frequency adjusting circuit adjusts the conversion parameter according to the first frequency offset when the first frequency offset is not within a first predetermined range such that a second frequency offset of a target frequency relative to a second predetermined frequency is within a second predetermined range.
    Type: Grant
    Filed: June 24, 2022
    Date of Patent: May 23, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chun-Chieh Chan, Tai-Jung Wu, Chia-Hao Chang
  • Patent number: 11658065
    Abstract: A method for CMP includes following operations. A metal layer is received. A CMP slurry composition is provided in a CMP apparatus. The CMP slurry composition includes at least a first oxidizer and a second oxidizer different from each other. The first oxidizer is oxidized to form a peroxidant by the second oxidizer. A portion of the metal layer is oxidized to form a first metal oxide by the peroxidant. The first metal oxide is re-oxidized to form a second metal oxide by the second oxidizer.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: May 23, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ji Cui, Fu-Ming Huang, Ting-Kui Chang, Tang-Kuei Chang, Chun-Chieh Lin, Wei-Wei Liang, Chi-Hsiang Shen, Ting-Hsun Chang, Li-Chieh Wu, Hung Yen, Chi-Jen Liu, Liang-Guang Chen, Kei-Wei Chen
  • Patent number: 11658599
    Abstract: A voltage measurement device for pulse-width modulation (PWM) signals is provided, which includes a conversion circuit and a processing circuit. The conversion circuit receives a first PWM signal and a second PWM signal from a motor driving device, and converts the first PWM signal and the second PWM signal into the absolute value signal and the polarity signal of the line-to-line voltage signal between the first PWM signal and the second PWM signal. The processing circuit converts the polarity signal and the absolute value signal into a first integral signal and a second integral signal, and reconstructs the line-to-line voltage signal according to the first integral signal and the second integral signal so as to obtain the reconstructed voltage signal of the line-to-line voltage signal.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: May 23, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Wen-Che Shen, Cheng-Min Chang, Chun-Chieh Chang, Po-Huan Chou
  • Publication number: 20230154998
    Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer.
    Type: Application
    Filed: January 23, 2023
    Publication date: May 18, 2023
    Inventors: Chun-Chieh LU, Carlos H. DIAZ, Chih-Sheng CHANG, Cheng-Yi PENG, Ling-Yen YEH
  • Publication number: 20230150438
    Abstract: An installing module includes a seat bracket, a plurality of lower gaskets, a device bracket and an upper gasket. The seat bracket includes a first locking plate and a second locking plate locked to each other. The first locking plate includes a first concave and the second locking plate includes a second concave corresponding to the first concave. The lower gaskets are respectively disposed on the first concave and the second concave. The lower gaskets face each other and jointly define a lower assembly hole and are disposed on a lower side of a head-support fixer of a car seat. The device bracket is locked to the seat bracket and an electronic device is pivotally coupled to the device bracket. The upper gasket is disposed between the device bracket and the head-support fixer, and the head-support fixer is clamped between the upper gasket and the lower gaskets.
    Type: Application
    Filed: August 26, 2022
    Publication date: May 18, 2023
    Applicant: PEGATRON CORPORATION
    Inventors: Shih-Wei Yeh, Chien-Chih Lin, Yi-Ming Chou, Chun-Chieh Chang
  • Publication number: 20230141521
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.
    Type: Application
    Filed: January 2, 2023
    Publication date: May 11, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yu LIN, Chi-Yu Chou, Hsien-Ming Lee, Huai-Tei Yang, Chun-Chieh Wang, Yueh-Ching Pai, Chi-Jen Yang, Tsung-Ta Tang, Yi-Ting Wang
  • Publication number: 20230141631
    Abstract: An aluminum battery separator applied between a positive electrode and a negative electrode of an aluminum battery includes a polymer material layer. An electrolyte is included between the positive electrode and the negative electrode of the aluminum battery. The polymer material layer includes one or more polymer materials, and the aluminum battery separator does not include a glass fiber material.
    Type: Application
    Filed: November 8, 2022
    Publication date: May 11, 2023
    Applicant: APh ePower Co., Ltd.
    Inventors: Jui-Hsuan Wu, Li-Hsien Chou, Chun-Chieh Yang